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| author | Aditya Minocha | 2024-08-25 21:38:12 +0530 |
|---|---|---|
| committer | GitHub | 2024-08-25 21:38:12 +0530 |
| commit | 0cc5a5f7833aa0fc6aa88bddaec4771d95cf4bad (patch) | |
| tree | aadde3f4dcef4aff01f7a7ad1b8308f495387c8f /SN54HC148/OR.cir | |
| parent | 55568c864d1f19971c15c27df999ea161a07f366 (diff) | |
| download | eSim-0cc5a5f7833aa0fc6aa88bddaec4771d95cf4bad.tar.gz eSim-0cc5a5f7833aa0fc6aa88bddaec4771d95cf4bad.tar.bz2 eSim-0cc5a5f7833aa0fc6aa88bddaec4771d95cf4bad.zip | |
SN54HC148 IC- 8:3 Priority Encoder
Diffstat (limited to 'SN54HC148/OR.cir')
| -rw-r--r-- | SN54HC148/OR.cir | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/SN54HC148/OR.cir b/SN54HC148/OR.cir new file mode 100644 index 00000000..65aebcbb --- /dev/null +++ b/SN54HC148/OR.cir @@ -0,0 +1,17 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\OR\OR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/28/24 22:45:53
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n
+M4 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n
+M5 Net-_M5-Pad1_ Net-_M1-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n
+M3 Net-_M2-Pad3_ Net-_M3-Pad2_ Net-_M1-Pad1_ Net-_M2-Pad3_ mosfet_p
+M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad1_ mosfet_p
+M6 Net-_M2-Pad1_ Net-_M1-Pad1_ Net-_M5-Pad1_ Net-_M2-Pad1_ mosfet_p
+U1 Net-_M1-Pad2_ Net-_M3-Pad2_ Net-_M5-Pad1_ Net-_M2-Pad1_ Net-_M1-Pad3_ PORT
+
+.end
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