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| author | Fahim | 2015-12-30 12:31:05 +0530 |
|---|---|---|
| committer | Fahim | 2015-12-30 12:31:05 +0530 |
| commit | 206afcded42d55572509e3439d752c9a81c84785 (patch) | |
| tree | 73ef64eda8504c27d6f1a3b1e141ee8d6efbbbe8 /Examples/fullwaverec/scr.cir.out | |
| parent | 06036bffa314d41f31cbdcd6883c9b3558930326 (diff) | |
| download | eSim-206afcded42d55572509e3439d752c9a81c84785.tar.gz eSim-206afcded42d55572509e3439d752c9a81c84785.tar.bz2 eSim-206afcded42d55572509e3439d752c9a81c84785.zip | |
Added :
1. Power Examples
2. eSim_Power.lib
3. DeviceModel for Powerdiode and Zenerdiode
4. Subcicuit for scr, diac, triac
Diffstat (limited to 'Examples/fullwaverec/scr.cir.out')
| -rw-r--r-- | Examples/fullwaverec/scr.cir.out | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/Examples/fullwaverec/scr.cir.out b/Examples/fullwaverec/scr.cir.out new file mode 100644 index 00000000..b01ee0bc --- /dev/null +++ b/Examples/fullwaverec/scr.cir.out @@ -0,0 +1,29 @@ +* /opt/esim/src/subcircuitlibrary/scr/scr.cir + +.include PowerDiode.lib +* u2 3 5 1 port +* f2 +d1 8 2 PowerDiode +c1 3 4 10u +r2 3 4 1 +* f1 +r1 5 6 50 +v1 6 7 dc 0 +v2 9 8 dc 0 +* u1 4 1 9 aswitch +Vf2 2 3 0 +f2 3 4 Vf2 100 +Vf1 7 3 0 +f1 3 4 Vf1 10 +a1 4 [1 9 ] u1 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 ) +.tran 0e-12 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |