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| author | Fahim | 2015-12-30 12:31:05 +0530 |
|---|---|---|
| committer | Fahim | 2015-12-30 12:31:05 +0530 |
| commit | 206afcded42d55572509e3439d752c9a81c84785 (patch) | |
| tree | 73ef64eda8504c27d6f1a3b1e141ee8d6efbbbe8 /Examples/fullwaverec/scr.cir.ckt | |
| parent | 06036bffa314d41f31cbdcd6883c9b3558930326 (diff) | |
| download | eSim-206afcded42d55572509e3439d752c9a81c84785.tar.gz eSim-206afcded42d55572509e3439d752c9a81c84785.tar.bz2 eSim-206afcded42d55572509e3439d752c9a81c84785.zip | |
Added :
1. Power Examples
2. eSim_Power.lib
3. DeviceModel for Powerdiode and Zenerdiode
4. Subcicuit for scr, diac, triac
Diffstat (limited to 'Examples/fullwaverec/scr.cir.ckt')
| -rw-r--r-- | Examples/fullwaverec/scr.cir.ckt | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/Examples/fullwaverec/scr.cir.ckt b/Examples/fullwaverec/scr.cir.ckt new file mode 100644 index 00000000..b0e218fd --- /dev/null +++ b/Examples/fullwaverec/scr.cir.ckt @@ -0,0 +1,19 @@ +* eeschema netlist version 1.1 (spice format) creation date: 08/21/14 11:07:22
+.include diode.lib
+
+u2 5 8 1 port
+* f2
+* Analog Switch analogswitch
+d1 4 2 diode
+v2 3 4 dc 0
+c1 5 6 10u
+r2 5 6 1
+* f1
+v1 9 7 dc 0
+r1 8 9 50
+Vf2 2 5 0
+f2 5 6 Vf2 100
+Vf1 7 5 0
+f1 5 6 Vf1 10
+a1 6 (1 3) u1
+.model u1 aswitch(cntl_on=0.25 cntl_off=0.1 r_on=0.0125 r_off=1000000)
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