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| author | Fahim | 2015-12-30 12:20:39 +0530 |
|---|---|---|
| committer | Fahim | 2015-12-30 12:20:39 +0530 |
| commit | 5c21ac87792c7eee763afcd6df80fc0bb8524b6c (patch) | |
| tree | 385a811388f218bc5ebd798a7b9bbbdfda537d1a /Examples/fullwaverec/fullwaverec.cir.ckt | |
| parent | e4b74bcbaa07bfe96f808db4d9fe6e05c6cde87d (diff) | |
| download | eSim-5c21ac87792c7eee763afcd6df80fc0bb8524b6c.tar.gz eSim-5c21ac87792c7eee763afcd6df80fc0bb8524b6c.tar.bz2 eSim-5c21ac87792c7eee763afcd6df80fc0bb8524b6c.zip | |
Added :
1. Power Examples
2. eSim_Power.lib
3. Subcircuit for diac, scr, triac
4. Device model for Power Diode
Diffstat (limited to 'Examples/fullwaverec/fullwaverec.cir.ckt')
| -rw-r--r-- | Examples/fullwaverec/fullwaverec.cir.ckt | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/Examples/fullwaverec/fullwaverec.cir.ckt b/Examples/fullwaverec/fullwaverec.cir.ckt new file mode 100644 index 00000000..22b8d7ce --- /dev/null +++ b/Examples/fullwaverec/fullwaverec.cir.ckt @@ -0,0 +1,16 @@ +* eeschema netlist version 1.1 (spice format) creation date: 09/08/14 10:24:20
+.include diode.lib
+.include scr.sub
+
+v1 1 2 sine(0 200 100 0 0)
+v2 4 0 pulse(0 5 2m 0 0 1m 5m)
+r1 5 3 500
+x1 0 4 5 scr
+d4 0 2 diode
+d3 2 3 diode
+d2 0 1 diode
+d1 1 3 diode
+
+.tran 10e-06 20e-03 0e-00
+.plot v(1)-v(2) v(3)-v(5)
+.end
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