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| author | Rahul P | 2020-08-08 19:16:28 +0530 |
|---|---|---|
| committer | GitHub | 2020-08-08 19:16:28 +0530 |
| commit | 8255c72075ab3541e8b6cfa7facb4e016157a905 (patch) | |
| tree | e86226cc6a609e54133b527ad71912996360722b /Examples/Mixed_Signal/Cmosinverter/Cmosinverter.cir | |
| parent | 175208c2553bde875968a9bc53176b6039ba9360 (diff) | |
| parent | 7871e58975d75eb2b02928f7a48d29113bebeb2b (diff) | |
| download | eSim-8255c72075ab3541e8b6cfa7facb4e016157a905.tar.gz eSim-8255c72075ab3541e8b6cfa7facb4e016157a905.tar.bz2 eSim-8255c72075ab3541e8b6cfa7facb4e016157a905.zip | |
Merge pull request #156 from rahulp13/master
ported GUI to PyQt5; platform independent paths; launch ngspice through mintty on Win OS
Diffstat (limited to 'Examples/Mixed_Signal/Cmosinverter/Cmosinverter.cir')
| -rw-r--r-- | Examples/Mixed_Signal/Cmosinverter/Cmosinverter.cir | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/Examples/Mixed_Signal/Cmosinverter/Cmosinverter.cir b/Examples/Mixed_Signal/Cmosinverter/Cmosinverter.cir new file mode 100644 index 00000000..7736c9d0 --- /dev/null +++ b/Examples/Mixed_Signal/Cmosinverter/Cmosinverter.cir @@ -0,0 +1,26 @@ +* /home/saurabh/eSim-Workspace/Cmosinvertor/Cmosinvertor.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Nov 27 14:17:36 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 out1 plot_v1 +X1 out7 out1 INVCMOS +X2 out1 out2 INVCMOS +X3 out2 out3 INVCMOS +U3 out2 plot_v1 +U4 out3 plot_v1 +X4 out3 out4 INVCMOS +U5 out4 plot_v1 +X5 out4 out5 INVCMOS +U6 out5 plot_v1 +X6 out5 out6 INVCMOS +U7 out6 plot_v1 +U8 out7 plot_v1 +U9 out6 Net-_U1-Pad1_ adc_bridge_1 +U10 Net-_U1-Pad2_ out7 dac_bridge_1 +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ inverter + +.end |