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author | rahulp13 | 2020-02-14 15:16:35 +0530 |
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committer | rahulp13 | 2020-02-14 15:16:35 +0530 |
commit | cb55e59de7ee4383c04edfae7c39ad9ae9552b36 (patch) | |
tree | de1b292a10e8196689bf1a208fe6fe32f4618846 /Examples/HalfAdder/half_adder.cir | |
parent | 08d4a0336550a0e610709970a0c5d366e109fe82 (diff) | |
download | eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.tar.gz eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.tar.bz2 eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.zip |
common code for Win and Linux, merged py2 changes
Diffstat (limited to 'Examples/HalfAdder/half_adder.cir')
-rw-r--r-- | Examples/HalfAdder/half_adder.cir | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/Examples/HalfAdder/half_adder.cir b/Examples/HalfAdder/half_adder.cir deleted file mode 100644 index 8b2e7e06..00000000 --- a/Examples/HalfAdder/half_adder.cir +++ /dev/null @@ -1,11 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U2 1 4 3 d_xor -U3 1 4 2 d_and -U1 1 4 3 2 PORT - -.end |