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authorrahulp132020-02-14 15:16:35 +0530
committerrahulp132020-02-14 15:16:35 +0530
commitcb55e59de7ee4383c04edfae7c39ad9ae9552b36 (patch)
treede1b292a10e8196689bf1a208fe6fe32f4618846 /Examples/HalfAdder/half_adder.cir
parent08d4a0336550a0e610709970a0c5d366e109fe82 (diff)
downloadeSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.tar.gz
eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.tar.bz2
eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.zip
common code for Win and Linux, merged py2 changes
Diffstat (limited to 'Examples/HalfAdder/half_adder.cir')
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diff --git a/Examples/HalfAdder/half_adder.cir b/Examples/HalfAdder/half_adder.cir
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-* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-*Sheet Name:/
-U2 1 4 3 d_xor
-U3 1 4 2 d_and
-U1 1 4 3 2 PORT
-
-.end