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authorSunil Shetye2019-03-12 12:30:33 +0530
committerSunil Shetye2019-07-01 18:04:00 +0530
commit7b559bc99379a475866479137f3ee2ed4dfbab86 (patch)
treeb397dbdf6d63632ee48741010e9019b0dc77669c /Examples/FullwaveRectifier_SCR
parentd2b775bde7bde4396c251ddac6685d503d0577d8 (diff)
downloadeSim-7b559bc99379a475866479137f3ee2ed4dfbab86.tar.gz
eSim-7b559bc99379a475866479137f3ee2ed4dfbab86.tar.bz2
eSim-7b559bc99379a475866479137f3ee2ed4dfbab86.zip
remove extra + at the start
Diffstat (limited to 'Examples/FullwaveRectifier_SCR')
-rw-r--r--Examples/FullwaveRectifier_SCR/D.lib21
-rw-r--r--Examples/FullwaveRectifier_SCR/PowerDiode.lib21
2 files changed, 2 insertions, 40 deletions
diff --git a/Examples/FullwaveRectifier_SCR/D.lib b/Examples/FullwaveRectifier_SCR/D.lib
index ef18bb50..89b96f4a 100644
--- a/Examples/FullwaveRectifier_SCR/D.lib
+++ b/Examples/FullwaveRectifier_SCR/D.lib
@@ -1,20 +1 @@
-.MODEL D1N750 D(
-+ Vj=.75
-+ Nbvl=14.976
-+ Cjo=175p
-+ Rs=.25
-+ Isr=1.859n
-+ Eg=1.11
-+ M=.5516
-+ Nbv=1.6989
-+ N=1
-+ Tbv1=-21.277u
-+ Bv=8.1
-+ Fc=.5
-+ Ikf=0
-+ Nr=2
-+ Ibv=20.245m
-+ Is=880.5E-18
-+ Xti=3
-+ Ibvl=1.9556m
-) \ No newline at end of file
+.MODEL D1N750 D( Vj=.75 Nbvl=14.976 Cjo=175p Rs=.25 Isr=1.859n Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u Bv=8.1 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m Is=880.5E-18 Xti=3 Ibvl=1.9556m )
diff --git a/Examples/FullwaveRectifier_SCR/PowerDiode.lib b/Examples/FullwaveRectifier_SCR/PowerDiode.lib
index a2f61dce..d6fb6469 100644
--- a/Examples/FullwaveRectifier_SCR/PowerDiode.lib
+++ b/Examples/FullwaveRectifier_SCR/PowerDiode.lib
@@ -1,20 +1 @@
-.MODEL PowerDiode D(
-+ Vj=.75
-+ Nbvl=14.976
-+ Cjo=175p
-+ Rs=.25
-+ Isr=1.859n
-+ Eg=1.11
-+ M=.5516
-+ Nbv=1.6989
-+ N=1
-+ Tbv1=-21.277u
-+ bv=1800
-+ Fc=.5
-+ Ikf=0
-+ Nr=2
-+ Ibv=20.245m
-+ Is=2.2E-15
-+ Xti=3
-+ Ibvl=1.9556m
-) \ No newline at end of file
+.MODEL PowerDiode D( Vj=.75 Nbvl=14.976 Cjo=175p Rs=.25 Isr=1.859n Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u bv=1800 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m Is=2.2E-15 Xti=3 Ibvl=1.9556m )