diff options
| author | fahim | 2015-08-05 13:52:57 +0530 |
|---|---|---|
| committer | fahim | 2015-08-05 13:52:57 +0530 |
| commit | df569f79a7ee495291324e07d99af990104e3db2 (patch) | |
| tree | a005c682aa78b58b7dd5bb693c415eff9c04d04b /Examples/Full_Adder | |
| parent | c4971ed867af4a970a3cd1c23825adee5073372e (diff) | |
| download | eSim-df569f79a7ee495291324e07d99af990104e3db2.tar.gz eSim-df569f79a7ee495291324e07d99af990104e3db2.tar.bz2 eSim-df569f79a7ee495291324e07d99af990104e3db2.zip | |
Subject: Added eSim Examples
Description: Added eSim Examples
Diffstat (limited to 'Examples/Full_Adder')
25 files changed, 1671 insertions, 0 deletions
diff --git a/Examples/Full_Adder/Full_Adder-cache.lib b/Examples/Full_Adder/Full_Adder-cache.lib new file mode 100644 index 00000000..8bbd82d9 --- /dev/null +++ b/Examples/Full_Adder/Full_Adder-cache.lib @@ -0,0 +1,116 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 95 50 H I C CNN +F1 "PWR_FLAG" 0 180 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 30 V V C CNN +F3 "" 0 0 30 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 60 60 1 1 P +X ~ 2 0 -150 50 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# adc_bridge_3 +# +DEF adc_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_2 +# +DEF dac_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_2" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -250 200 350 -100 0 1 0 N +X IN1 1 -450 50 200 R 50 50 1 1 I +X IN2 2 -450 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT4 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# full_adder +# +DEF full_adder X 0 40 Y Y 1 F N +F0 "X" 1400 700 60 H V C CNN +F1 "full_adder" 1400 600 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 800 1150 1950 0 0 1 0 N +X IN1 1 600 950 200 R 50 50 1 1 I +X IN2 2 600 550 200 R 50 50 1 1 I +X CIN 3 600 150 200 R 50 50 1 1 I +X SUM 4 2150 950 200 L 50 50 1 1 O +X COUT 5 2150 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Full_Adder/Full_Adder.bak b/Examples/Full_Adder/Full_Adder.bak new file mode 100644 index 00000000..ee676616 --- /dev/null +++ b/Examples/Full_Adder/Full_Adder.bak @@ -0,0 +1,243 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L full_adder X1 +U 1 1 558AA02B +P 4700 4500 +F 0 "X1" H 6100 5200 60 0000 C CNN +F 1 "full_adder" H 6100 5100 60 0000 C CNN +F 2 "" H 4700 4500 60 0000 C CNN +F 3 "" H 4700 4500 60 0000 C CNN + 1 4700 4500 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_3 U1 +U 1 1 558AA1CF +P 4200 3950 +F 0 "U1" H 4200 3950 60 0000 C CNN +F 1 "adc_bridge_3" H 4200 4100 60 0000 C CNN +F 2 "" H 4200 3950 60 0000 C CNN +F 3 "" H 4200 3950 60 0000 C CNN + 1 4200 3950 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_2 U2 +U 1 1 558AA20A +P 7700 3950 +F 0 "U2" H 7700 3950 60 0000 C CNN +F 1 "dac_bridge_2" H 7750 4100 60 0000 C CNN +F 2 "" H 7700 3950 60 0000 C CNN +F 3 "" H 7700 3950 60 0000 C CNN + 1 7700 3950 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 558AA22C +P 8750 3800 +F 0 "R1" V 8830 3800 50 0000 C CNN +F 1 "1k" V 8750 3800 50 0000 C CNN +F 2 "" V 8680 3800 30 0000 C CNN +F 3 "" H 8750 3800 30 0000 C CNN + 1 8750 3800 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 558AA263 +P 8750 4100 +F 0 "R2" V 8830 4100 50 0000 C CNN +F 1 "1k" V 8750 4100 50 0000 C CNN +F 2 "" V 8680 4100 30 0000 C CNN +F 3 "" H 8750 4100 30 0000 C CNN + 1 8750 4100 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR01 +U 1 1 558AA2B7 +P 9200 4150 +F 0 "#PWR01" H 9200 4150 30 0001 C CNN +F 1 "GND" H 9200 4080 30 0001 C CNN +F 2 "" H 9200 4150 60 0000 C CNN +F 3 "" H 9200 4150 60 0000 C CNN + 1 9200 4150 + 1 0 0 -1 +$EndComp +$Comp +L DC v3 +U 1 1 558AA2E9 +P 2900 3550 +F 0 "v3" H 2700 3650 60 0000 C CNN +F 1 "DC" H 2700 3500 60 0000 C CNN +F 2 "R1" H 2600 3550 60 0000 C CNN +F 3 "" H 2900 3550 60 0000 C CNN + 1 2900 3550 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 558AA31A +P 2700 4000 +F 0 "v1" H 2500 4100 60 0000 C CNN +F 1 "DC" H 2500 3950 60 0000 C CNN +F 2 "R1" H 2400 4000 60 0000 C CNN +F 3 "" H 2700 4000 60 0000 C CNN + 1 2700 4000 + 0 1 1 0 +$EndComp +$Comp +L DC v2 +U 1 1 558AA356 +P 2800 4500 +F 0 "v2" H 2600 4600 60 0000 C CNN +F 1 "DC" H 2600 4450 60 0000 C CNN +F 2 "R1" H 2500 4500 60 0000 C CNN +F 3 "" H 2800 4500 60 0000 C CNN + 1 2800 4500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 558AA3F6 +P 2100 4750 +F 0 "#PWR02" H 2100 4750 30 0001 C CNN +F 1 "GND" H 2100 4680 30 0001 C CNN +F 2 "" H 2100 4750 60 0000 C CNN +F 3 "" H 2100 4750 60 0000 C CNN + 1 2100 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 3550 3350 3900 +Wire Wire Line + 3350 3900 3600 3900 +Wire Wire Line + 3150 4000 3600 4000 +Wire Wire Line + 3600 4100 3400 4100 +Wire Wire Line + 3400 4100 3400 4500 +Wire Wire Line + 3400 4500 3250 4500 +Wire Wire Line + 2450 3550 2100 3550 +Wire Wire Line + 2100 3550 2100 4750 +Wire Wire Line + 2350 4500 2100 4500 +Connection ~ 2100 4500 +Wire Wire Line + 2250 4000 2100 4000 +Connection ~ 2100 4000 +Wire Wire Line + 4750 3900 5000 3900 +Wire Wire Line + 5000 3900 5000 3550 +Wire Wire Line + 5000 3550 5300 3550 +Wire Wire Line + 4750 4000 5150 4000 +Wire Wire Line + 5150 4000 5150 3950 +Wire Wire Line + 5150 3950 5300 3950 +Wire Wire Line + 4750 4100 5300 4100 +Wire Wire Line + 5300 4100 5300 4350 +Wire Wire Line + 6850 3550 6850 3900 +Wire Wire Line + 6850 3900 7250 3900 +Wire Wire Line + 7250 4000 6850 4000 +Wire Wire Line + 6850 4000 6850 4350 +Wire Wire Line + 8250 3900 8400 3900 +Wire Wire Line + 8400 3900 8400 3800 +Wire Wire Line + 8400 3800 8600 3800 +Wire Wire Line + 8250 4000 8400 4000 +Wire Wire Line + 8400 4000 8400 4100 +Wire Wire Line + 8400 4100 8600 4100 +Wire Wire Line + 8900 3800 9200 3800 +Wire Wire Line + 9200 3800 9200 4150 +Wire Wire Line + 8900 4100 9200 4100 +Wire Wire Line + 9200 4100 9200 4050 +Connection ~ 9200 4050 +$Comp +L PWR_FLAG #FLG03 +U 1 1 558AA6B1 +P 9150 3600 +F 0 "#FLG03" H 9150 3695 50 0001 C CNN +F 1 "PWR_FLAG" H 9150 3780 50 0000 C CNN +F 2 "" H 9150 3600 60 0000 C CNN +F 3 "" H 9150 3600 60 0000 C CNN + 1 9150 3600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9150 3600 9150 3800 +Connection ~ 9150 3800 +$EndSCHEMATC diff --git a/Examples/Full_Adder/Full_Adder.cir b/Examples/Full_Adder/Full_Adder.cir new file mode 100644 index 00000000..f073381c --- /dev/null +++ b/Examples/Full_Adder/Full_Adder.cir @@ -0,0 +1,16 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 12:29:51 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +X1 4 3 2 1 8 full_adder +U1 10 11 9 4 3 2 adc_bridge_3 +U2 1 8 7 5 dac_bridge_2 +R1 0 7 1k +R2 0 5 1k +v3 10 0 DC +v1 11 0 DC +v2 9 0 DC + +.end diff --git a/Examples/Full_Adder/Full_Adder.cir.out b/Examples/Full_Adder/Full_Adder.cir.out new file mode 100644 index 00000000..803633a9 --- /dev/null +++ b/Examples/Full_Adder/Full_Adder.cir.out @@ -0,0 +1,26 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:29:51 2015 + +.include full_adder.sub +x1 4 3 2 1 8 full_adder +* u1 10 11 9 4 3 2 adc_bridge_3 +* u2 1 8 7 5 dac_bridge_2 +r1 0 7 1k +r2 0 5 1k +v3 10 0 dc 5 +v1 11 0 dc 0 +v2 9 0 dc 5 +a1 [10 11 9 ] [4 3 2 ] u1 +a2 [1 8 ] [7 5 ] u2 +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u2 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/Full_Adder/Full_Adder.pro b/Examples/Full_Adder/Full_Adder.pro new file mode 100644 index 00000000..c93c55b1 --- /dev/null +++ b/Examples/Full_Adder/Full_Adder.pro @@ -0,0 +1,69 @@ +update=Wed Jun 24 12:14:52 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/Examples/Full_Adder/Full_Adder.proj b/Examples/Full_Adder/Full_Adder.proj new file mode 100644 index 00000000..903f1923 --- /dev/null +++ b/Examples/Full_Adder/Full_Adder.proj @@ -0,0 +1 @@ +schematicFile Full_Adder.sch diff --git a/Examples/Full_Adder/Full_Adder.sch b/Examples/Full_Adder/Full_Adder.sch new file mode 100644 index 00000000..ee676616 --- /dev/null +++ b/Examples/Full_Adder/Full_Adder.sch @@ -0,0 +1,243 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L full_adder X1 +U 1 1 558AA02B +P 4700 4500 +F 0 "X1" H 6100 5200 60 0000 C CNN +F 1 "full_adder" H 6100 5100 60 0000 C CNN +F 2 "" H 4700 4500 60 0000 C CNN +F 3 "" H 4700 4500 60 0000 C CNN + 1 4700 4500 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_3 U1 +U 1 1 558AA1CF +P 4200 3950 +F 0 "U1" H 4200 3950 60 0000 C CNN +F 1 "adc_bridge_3" H 4200 4100 60 0000 C CNN +F 2 "" H 4200 3950 60 0000 C CNN +F 3 "" H 4200 3950 60 0000 C CNN + 1 4200 3950 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_2 U2 +U 1 1 558AA20A +P 7700 3950 +F 0 "U2" H 7700 3950 60 0000 C CNN +F 1 "dac_bridge_2" H 7750 4100 60 0000 C CNN +F 2 "" H 7700 3950 60 0000 C CNN +F 3 "" H 7700 3950 60 0000 C CNN + 1 7700 3950 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 558AA22C +P 8750 3800 +F 0 "R1" V 8830 3800 50 0000 C CNN +F 1 "1k" V 8750 3800 50 0000 C CNN +F 2 "" V 8680 3800 30 0000 C CNN +F 3 "" H 8750 3800 30 0000 C CNN + 1 8750 3800 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 558AA263 +P 8750 4100 +F 0 "R2" V 8830 4100 50 0000 C CNN +F 1 "1k" V 8750 4100 50 0000 C CNN +F 2 "" V 8680 4100 30 0000 C CNN +F 3 "" H 8750 4100 30 0000 C CNN + 1 8750 4100 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR01 +U 1 1 558AA2B7 +P 9200 4150 +F 0 "#PWR01" H 9200 4150 30 0001 C CNN +F 1 "GND" H 9200 4080 30 0001 C CNN +F 2 "" H 9200 4150 60 0000 C CNN +F 3 "" H 9200 4150 60 0000 C CNN + 1 9200 4150 + 1 0 0 -1 +$EndComp +$Comp +L DC v3 +U 1 1 558AA2E9 +P 2900 3550 +F 0 "v3" H 2700 3650 60 0000 C CNN +F 1 "DC" H 2700 3500 60 0000 C CNN +F 2 "R1" H 2600 3550 60 0000 C CNN +F 3 "" H 2900 3550 60 0000 C CNN + 1 2900 3550 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 558AA31A +P 2700 4000 +F 0 "v1" H 2500 4100 60 0000 C CNN +F 1 "DC" H 2500 3950 60 0000 C CNN +F 2 "R1" H 2400 4000 60 0000 C CNN +F 3 "" H 2700 4000 60 0000 C CNN + 1 2700 4000 + 0 1 1 0 +$EndComp +$Comp +L DC v2 +U 1 1 558AA356 +P 2800 4500 +F 0 "v2" H 2600 4600 60 0000 C CNN +F 1 "DC" H 2600 4450 60 0000 C CNN +F 2 "R1" H 2500 4500 60 0000 C CNN +F 3 "" H 2800 4500 60 0000 C CNN + 1 2800 4500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 558AA3F6 +P 2100 4750 +F 0 "#PWR02" H 2100 4750 30 0001 C CNN +F 1 "GND" H 2100 4680 30 0001 C CNN +F 2 "" H 2100 4750 60 0000 C CNN +F 3 "" H 2100 4750 60 0000 C CNN + 1 2100 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 3550 3350 3900 +Wire Wire Line + 3350 3900 3600 3900 +Wire Wire Line + 3150 4000 3600 4000 +Wire Wire Line + 3600 4100 3400 4100 +Wire Wire Line + 3400 4100 3400 4500 +Wire Wire Line + 3400 4500 3250 4500 +Wire Wire Line + 2450 3550 2100 3550 +Wire Wire Line + 2100 3550 2100 4750 +Wire Wire Line + 2350 4500 2100 4500 +Connection ~ 2100 4500 +Wire Wire Line + 2250 4000 2100 4000 +Connection ~ 2100 4000 +Wire Wire Line + 4750 3900 5000 3900 +Wire Wire Line + 5000 3900 5000 3550 +Wire Wire Line + 5000 3550 5300 3550 +Wire Wire Line + 4750 4000 5150 4000 +Wire Wire Line + 5150 4000 5150 3950 +Wire Wire Line + 5150 3950 5300 3950 +Wire Wire Line + 4750 4100 5300 4100 +Wire Wire Line + 5300 4100 5300 4350 +Wire Wire Line + 6850 3550 6850 3900 +Wire Wire Line + 6850 3900 7250 3900 +Wire Wire Line + 7250 4000 6850 4000 +Wire Wire Line + 6850 4000 6850 4350 +Wire Wire Line + 8250 3900 8400 3900 +Wire Wire Line + 8400 3900 8400 3800 +Wire Wire Line + 8400 3800 8600 3800 +Wire Wire Line + 8250 4000 8400 4000 +Wire Wire Line + 8400 4000 8400 4100 +Wire Wire Line + 8400 4100 8600 4100 +Wire Wire Line + 8900 3800 9200 3800 +Wire Wire Line + 9200 3800 9200 4150 +Wire Wire Line + 8900 4100 9200 4100 +Wire Wire Line + 9200 4100 9200 4050 +Connection ~ 9200 4050 +$Comp +L PWR_FLAG #FLG03 +U 1 1 558AA6B1 +P 9150 3600 +F 0 "#FLG03" H 9150 3695 50 0001 C CNN +F 1 "PWR_FLAG" H 9150 3780 50 0000 C CNN +F 2 "" H 9150 3600 60 0000 C CNN +F 3 "" H 9150 3600 60 0000 C CNN + 1 9150 3600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9150 3600 9150 3800 +Connection ~ 9150 3800 +$EndSCHEMATC diff --git a/Examples/Full_Adder/Full_Adder_Previous_Values.xml b/Examples/Full_Adder/Full_Adder_Previous_Values.xml new file mode 100644 index 00000000..5e07a756 --- /dev/null +++ b/Examples/Full_Adder/Full_Adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source><v3 name="Source type">dc<field1 name="Value">5</field1></v3><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v2 name="Source type">dc<field1 name="Value">5</field1></v2></source><model><u1 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter value for in_low (default=1.0)" /></u1><u2 name="type">dac_bridge<field5 name="Enter value for input load (default=1.0e-12)" /><field6 name="Enter value for out_low (default=0.0)" /><field7 name="Enter value for out_high (default=5.0)" /><field8 name="Enter the Rise Time (default=1.0e-9)" /><field9 name="Enter the Fall Time (default=1.0e-9)" /><field10 name="Enter value for out_undef (default=0.5)" /></u2></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Full_Adder/analysis b/Examples/Full_Adder/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/Full_Adder/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/Examples/Full_Adder/full_adder-cache.lib b/Examples/Full_Adder/full_adder-cache.lib new file mode 100644 index 00000000..623a7f41 --- /dev/null +++ b/Examples/Full_Adder/full_adder-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Full_Adder/full_adder.cir b/Examples/Full_Adder/full_adder.cir new file mode 100644 index 00000000..6461b5b6 --- /dev/null +++ b/Examples/Full_Adder/full_adder.cir @@ -0,0 +1,12 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 12:24:33 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +X1 8 7 6 2 half_adder +X2 5 6 4 3 half_adder +U1 8 7 5 4 1 PORT +U2 3 2 1 d_or + +.end diff --git a/Examples/Full_Adder/full_adder.cir.out b/Examples/Full_Adder/full_adder.cir.out new file mode 100644 index 00000000..b90ce70d --- /dev/null +++ b/Examples/Full_Adder/full_adder.cir.out @@ -0,0 +1,19 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 + +.include half_adder.sub +x1 8 7 6 2 half_adder +x2 5 6 4 3 half_adder +* u1 8 7 5 4 1 port +* u2 3 2 1 d_or +a1 [3 2 ] 1 u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/Full_Adder/full_adder.pro b/Examples/Full_Adder/full_adder.pro new file mode 100644 index 00000000..c0db0775 --- /dev/null +++ b/Examples/Full_Adder/full_adder.pro @@ -0,0 +1,69 @@ +update=Wed Jun 24 12:19:16 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/Examples/Full_Adder/full_adder.sch b/Examples/Full_Adder/full_adder.sch new file mode 100644 index 00000000..8bd400f2 --- /dev/null +++ b/Examples/Full_Adder/full_adder.sch @@ -0,0 +1,180 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L half_adder X1 +U 1 1 558AA064 +P 3800 3350 +F 0 "X1" H 4700 3850 60 0000 C CNN +F 1 "half_adder" H 4700 3750 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L half_adder X2 +U 1 1 558AA0C1 +P 5700 3350 +F 0 "X2" H 6600 3850 60 0000 C CNN +F 1 "half_adder" H 6600 3750 60 0000 C CNN +F 2 "" H 5700 3350 60 0000 C CNN +F 3 "" H 5700 3350 60 0000 C CNN + 1 5700 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558AA277 +P 3450 2650 +F 0 "U1" H 3500 2750 30 0000 C CNN +F 1 "PORT" H 3450 2650 30 0000 C CNN +F 2 "" H 3450 2650 60 0000 C CNN +F 3 "" H 3450 2650 60 0000 C CNN + 1 3450 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558AA29E +P 3450 3250 +F 0 "U1" H 3500 3350 30 0000 C CNN +F 1 "PORT" H 3450 3250 30 0000 C CNN +F 2 "" H 3450 3250 60 0000 C CNN +F 3 "" H 3450 3250 60 0000 C CNN + 2 3450 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558AA2D8 +P 5650 2300 +F 0 "U1" H 5700 2400 30 0000 C CNN +F 1 "PORT" H 5650 2300 30 0000 C CNN +F 2 "" H 5650 2300 60 0000 C CNN +F 3 "" H 5650 2300 60 0000 C CNN + 3 5650 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 558AA378 +P 7900 2650 +F 0 "U1" H 7950 2750 30 0000 C CNN +F 1 "PORT" H 7900 2650 30 0000 C CNN +F 2 "" H 7900 2650 60 0000 C CNN +F 3 "" H 7900 2650 60 0000 C CNN + 4 7900 2650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 558AA3E0 +P 8700 3400 +F 0 "U1" H 8750 3500 30 0000 C CNN +F 1 "PORT" H 8700 3400 30 0000 C CNN +F 2 "" H 8700 3400 60 0000 C CNN +F 3 "" H 8700 3400 60 0000 C CNN + 5 8700 3400 + -1 0 0 1 +$EndComp +$Comp +L d_or U2 +U 1 1 558AA43B +P 7900 3450 +F 0 "U2" H 7900 3450 60 0000 C CNN +F 1 "d_or" H 7900 3550 60 0000 C CNN +F 2 "" H 7900 3450 60 0000 C CNN +F 3 "" H 7900 3450 60 0000 C CNN + 1 7900 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3700 2650 4100 2650 +Wire Wire Line + 3700 3250 4100 3250 +Wire Wire Line + 5250 2650 5650 2650 +Wire Wire Line + 5650 2650 5650 3250 +Wire Wire Line + 5650 3250 6000 3250 +Wire Wire Line + 5900 2300 5900 2650 +Wire Wire Line + 5900 2650 6000 2650 +Wire Wire Line + 7150 2650 7650 2650 +Wire Wire Line + 7150 3250 7350 3250 +Wire Wire Line + 7350 3250 7350 3350 +Wire Wire Line + 7350 3350 7450 3350 +Wire Wire Line + 5250 3250 5400 3250 +Wire Wire Line + 5400 3250 5400 3450 +Wire Wire Line + 5400 3450 7450 3450 +Wire Wire Line + 8350 3400 8450 3400 +Text Notes 3850 2500 0 60 ~ 0 +IN1 +Text Notes 3850 3150 0 60 ~ 0 +IN2 +Text Notes 6000 2350 0 60 ~ 0 +CIN +Text Notes 7350 2550 0 60 ~ 0 +SUM +Text Notes 8300 3200 0 60 ~ 0 +COUT +$EndSCHEMATC diff --git a/Examples/Full_Adder/full_adder.sub b/Examples/Full_Adder/full_adder.sub new file mode 100644 index 00000000..5f261f78 --- /dev/null +++ b/Examples/Full_Adder/full_adder.sub @@ -0,0 +1,13 @@ +* Subcircuit full_adder +.subckt full_adder 8 7 5 4 1 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 +.include half_adder.sub +x1 8 7 6 2 half_adder +x2 5 6 4 3 half_adder +* u2 3 2 1 d_or +a1 [3 2 ] 1 u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends full_adder
\ No newline at end of file diff --git a/Examples/Full_Adder/full_adder_Previous_Values.xml b/Examples/Full_Adder/full_adder_Previous_Values.xml new file mode 100644 index 00000000..b63184d6 --- /dev/null +++ b/Examples/Full_Adder/full_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Full_Adder/half_adder-cache.lib b/Examples/Full_Adder/half_adder-cache.lib new file mode 100644 index 00000000..68785220 --- /dev/null +++ b/Examples/Full_Adder/half_adder-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Full_Adder/half_adder.cir b/Examples/Full_Adder/half_adder.cir new file mode 100644 index 00000000..8b2e7e06 --- /dev/null +++ b/Examples/Full_Adder/half_adder.cir @@ -0,0 +1,11 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 1 4 3 d_xor +U3 1 4 2 d_and +U1 1 4 3 2 PORT + +.end diff --git a/Examples/Full_Adder/half_adder.cir.out b/Examples/Full_Adder/half_adder.cir.out new file mode 100644 index 00000000..b1b6b1e7 --- /dev/null +++ b/Examples/Full_Adder/half_adder.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 + +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +* u1 1 4 3 2 port +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/Full_Adder/half_adder.pro b/Examples/Full_Adder/half_adder.pro new file mode 100644 index 00000000..695ae0f6 --- /dev/null +++ b/Examples/Full_Adder/half_adder.pro @@ -0,0 +1,69 @@ +update=Wed Jun 24 11:27:22 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/Examples/Full_Adder/half_adder.sch b/Examples/Full_Adder/half_adder.sch new file mode 100644 index 00000000..bf9bcbf0 --- /dev/null +++ b/Examples/Full_Adder/half_adder.sch @@ -0,0 +1,152 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U2 +U 1 1 558A946A +P 5650 3050 +F 0 "U2" H 5650 3050 60 0000 C CNN +F 1 "d_xor" H 5700 3150 47 0000 C CNN +F 2 "" H 5650 3050 60 0000 C CNN +F 3 "" H 5650 3050 60 0000 C CNN + 1 5650 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 558A94D5 +P 5700 3800 +F 0 "U3" H 5700 3800 60 0000 C CNN +F 1 "d_and" H 5750 3900 60 0000 C CNN +F 2 "" H 5700 3800 60 0000 C CNN +F 3 "" H 5700 3800 60 0000 C CNN + 1 5700 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558A94F6 +P 4150 3000 +F 0 "U1" H 4200 3100 30 0000 C CNN +F 1 "PORT" H 4150 3000 30 0000 C CNN +F 2 "" H 4150 3000 60 0000 C CNN +F 3 "" H 4150 3000 60 0000 C CNN + 1 4150 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558A9543 +P 4150 3450 +F 0 "U1" H 4200 3550 30 0000 C CNN +F 1 "PORT" H 4150 3450 30 0000 C CNN +F 2 "" H 4150 3450 60 0000 C CNN +F 3 "" H 4150 3450 60 0000 C CNN + 2 4150 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558A9573 +P 6650 3000 +F 0 "U1" H 6700 3100 30 0000 C CNN +F 1 "PORT" H 6650 3000 30 0000 C CNN +F 2 "" H 6650 3000 60 0000 C CNN +F 3 "" H 6650 3000 60 0000 C CNN + 3 6650 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 558A9606 +P 6700 3750 +F 0 "U1" H 6750 3850 30 0000 C CNN +F 1 "PORT" H 6700 3750 30 0000 C CNN +F 2 "" H 6700 3750 60 0000 C CNN +F 3 "" H 6700 3750 60 0000 C CNN + 4 6700 3750 + -1 0 0 1 +$EndComp +Wire Wire Line + 5200 2950 4450 2950 +Wire Wire Line + 4450 2950 4450 3000 +Wire Wire Line + 4450 3000 4400 3000 +Wire Wire Line + 4400 3450 4550 3450 +Wire Wire Line + 4550 3450 4550 3050 +Wire Wire Line + 4550 3050 5200 3050 +Wire Wire Line + 5250 3700 5000 3700 +Wire Wire Line + 5000 3700 5000 2950 +Connection ~ 5000 2950 +Wire Wire Line + 5250 3800 4850 3800 +Wire Wire Line + 4850 3800 4850 3050 +Connection ~ 4850 3050 +Wire Wire Line + 6100 3000 6400 3000 +Wire Wire Line + 6150 3750 6450 3750 +Text Notes 4550 2950 0 60 ~ 0 +IN1\n\n +Text Notes 4600 3150 0 60 ~ 0 +IN2 +Text Notes 6200 2950 0 60 ~ 0 +SUM\n +Text Notes 6200 3650 0 60 ~ 0 +COUT\n +$EndSCHEMATC diff --git a/Examples/Full_Adder/half_adder.sub b/Examples/Full_Adder/half_adder.sub new file mode 100644 index 00000000..e9f92223 --- /dev/null +++ b/Examples/Full_Adder/half_adder.sub @@ -0,0 +1,14 @@ +* Subcircuit half_adder +.subckt half_adder 1 4 3 2 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_adder
\ No newline at end of file diff --git a/Examples/Full_Adder/half_adder_Previous_Values.xml b/Examples/Full_Adder/half_adder_Previous_Values.xml new file mode 100644 index 00000000..b915f0da --- /dev/null +++ b/Examples/Full_Adder/half_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Full_Adder/plot_data_i.txt b/Examples/Full_Adder/plot_data_i.txt new file mode 100644 index 00000000..0b3114d8 --- /dev/null +++ b/Examples/Full_Adder/plot_data_i.txt @@ -0,0 +1,135 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:29:51 2015 +Transient Analysis Tue Jun 30 14:47:07 2015 +-------------------------------------------------------------------------------- +Index time a2#branch_1_0 a2#branch_1_1 v1#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 -5.00000e-03 0.000000e+00 +1 1.000000e-05 0.000000e+00 -5.00000e-03 0.000000e+00 +2 2.000000e-05 0.000000e+00 -5.00000e-03 0.000000e+00 +3 4.000000e-05 0.000000e+00 -5.00000e-03 0.000000e+00 +4 8.000000e-05 0.000000e+00 -5.00000e-03 0.000000e+00 +5 1.600000e-04 0.000000e+00 -5.00000e-03 0.000000e+00 +6 3.200000e-04 0.000000e+00 -5.00000e-03 0.000000e+00 +7 6.400000e-04 0.000000e+00 -5.00000e-03 0.000000e+00 +8 1.280000e-03 0.000000e+00 -5.00000e-03 0.000000e+00 +9 2.560000e-03 0.000000e+00 -5.00000e-03 0.000000e+00 +10 4.560000e-03 0.000000e+00 -5.00000e-03 0.000000e+00 +11 6.560000e-03 0.000000e+00 -5.00000e-03 0.000000e+00 +12 8.560000e-03 0.000000e+00 -5.00000e-03 0.000000e+00 +13 1.056000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +14 1.256000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +15 1.456000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +16 1.656000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +17 1.856000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +18 2.056000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +19 2.256000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +20 2.456000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +21 2.656000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +22 2.856000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +23 3.056000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +24 3.256000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +25 3.456000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +26 3.656000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +27 3.856000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +28 4.056000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +29 4.256000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +30 4.456000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +31 4.656000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +32 4.856000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +33 5.056000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +34 5.256000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +35 5.456000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +36 5.656000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +37 5.856000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +38 6.056000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +39 6.256000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +40 6.456000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +41 6.656000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +42 6.856000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +43 7.056000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +44 7.256000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +45 7.456000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +46 7.656000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +47 7.856000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +48 8.056000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +49 8.256000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +50 8.456000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +51 8.656000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +52 8.856000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +53 9.056000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +54 9.256000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 + +Index time a2#branch_1_0 a2#branch_1_1 v1#branch +-------------------------------------------------------------------------------- +55 9.456000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +56 9.656000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +57 9.856000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +58 1.000000e-01 0.000000e+00 -5.00000e-03 0.000000e+00 + +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:29:51 2015 +Transient Analysis Tue Jun 30 14:47:07 2015 +-------------------------------------------------------------------------------- +Index time v2#branch v3#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-05 0.000000e+00 0.000000e+00 +2 2.000000e-05 0.000000e+00 0.000000e+00 +3 4.000000e-05 0.000000e+00 0.000000e+00 +4 8.000000e-05 0.000000e+00 0.000000e+00 +5 1.600000e-04 0.000000e+00 0.000000e+00 +6 3.200000e-04 0.000000e+00 0.000000e+00 +7 6.400000e-04 0.000000e+00 0.000000e+00 +8 1.280000e-03 0.000000e+00 0.000000e+00 +9 2.560000e-03 0.000000e+00 0.000000e+00 +10 4.560000e-03 0.000000e+00 0.000000e+00 +11 6.560000e-03 0.000000e+00 0.000000e+00 +12 8.560000e-03 0.000000e+00 0.000000e+00 +13 1.056000e-02 0.000000e+00 0.000000e+00 +14 1.256000e-02 0.000000e+00 0.000000e+00 +15 1.456000e-02 0.000000e+00 0.000000e+00 +16 1.656000e-02 0.000000e+00 0.000000e+00 +17 1.856000e-02 0.000000e+00 0.000000e+00 +18 2.056000e-02 0.000000e+00 0.000000e+00 +19 2.256000e-02 0.000000e+00 0.000000e+00 +20 2.456000e-02 0.000000e+00 0.000000e+00 +21 2.656000e-02 0.000000e+00 0.000000e+00 +22 2.856000e-02 0.000000e+00 0.000000e+00 +23 3.056000e-02 0.000000e+00 0.000000e+00 +24 3.256000e-02 0.000000e+00 0.000000e+00 +25 3.456000e-02 0.000000e+00 0.000000e+00 +26 3.656000e-02 0.000000e+00 0.000000e+00 +27 3.856000e-02 0.000000e+00 0.000000e+00 +28 4.056000e-02 0.000000e+00 0.000000e+00 +29 4.256000e-02 0.000000e+00 0.000000e+00 +30 4.456000e-02 0.000000e+00 0.000000e+00 +31 4.656000e-02 0.000000e+00 0.000000e+00 +32 4.856000e-02 0.000000e+00 0.000000e+00 +33 5.056000e-02 0.000000e+00 0.000000e+00 +34 5.256000e-02 0.000000e+00 0.000000e+00 +35 5.456000e-02 0.000000e+00 0.000000e+00 +36 5.656000e-02 0.000000e+00 0.000000e+00 +37 5.856000e-02 0.000000e+00 0.000000e+00 +38 6.056000e-02 0.000000e+00 0.000000e+00 +39 6.256000e-02 0.000000e+00 0.000000e+00 +40 6.456000e-02 0.000000e+00 0.000000e+00 +41 6.656000e-02 0.000000e+00 0.000000e+00 +42 6.856000e-02 0.000000e+00 0.000000e+00 +43 7.056000e-02 0.000000e+00 0.000000e+00 +44 7.256000e-02 0.000000e+00 0.000000e+00 +45 7.456000e-02 0.000000e+00 0.000000e+00 +46 7.656000e-02 0.000000e+00 0.000000e+00 +47 7.856000e-02 0.000000e+00 0.000000e+00 +48 8.056000e-02 0.000000e+00 0.000000e+00 +49 8.256000e-02 0.000000e+00 0.000000e+00 +50 8.456000e-02 0.000000e+00 0.000000e+00 +51 8.656000e-02 0.000000e+00 0.000000e+00 +52 8.856000e-02 0.000000e+00 0.000000e+00 +53 9.056000e-02 0.000000e+00 0.000000e+00 +54 9.256000e-02 0.000000e+00 0.000000e+00 + +Index time v2#branch v3#branch +-------------------------------------------------------------------------------- +55 9.456000e-02 0.000000e+00 0.000000e+00 +56 9.656000e-02 0.000000e+00 0.000000e+00 +57 9.856000e-02 0.000000e+00 0.000000e+00 +58 1.000000e-01 0.000000e+00 0.000000e+00 diff --git a/Examples/Full_Adder/plot_data_v.txt b/Examples/Full_Adder/plot_data_v.txt new file mode 100644 index 00000000..6cc6c40a --- /dev/null +++ b/Examples/Full_Adder/plot_data_v.txt @@ -0,0 +1,135 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:29:51 2015 +Transient Analysis Tue Jun 30 14:47:07 2015 +-------------------------------------------------------------------------------- +Index time V(5) V(7) V(9) +-------------------------------------------------------------------------------- +0 0.000000e+00 5.000000e+00 0.000000e+00 5.000000e+00 +1 1.000000e-05 5.000000e+00 0.000000e+00 5.000000e+00 +2 2.000000e-05 5.000000e+00 0.000000e+00 5.000000e+00 +3 4.000000e-05 5.000000e+00 0.000000e+00 5.000000e+00 +4 8.000000e-05 5.000000e+00 0.000000e+00 5.000000e+00 +5 1.600000e-04 5.000000e+00 0.000000e+00 5.000000e+00 +6 3.200000e-04 5.000000e+00 0.000000e+00 5.000000e+00 +7 6.400000e-04 5.000000e+00 0.000000e+00 5.000000e+00 +8 1.280000e-03 5.000000e+00 0.000000e+00 5.000000e+00 +9 2.560000e-03 5.000000e+00 0.000000e+00 5.000000e+00 +10 4.560000e-03 5.000000e+00 0.000000e+00 5.000000e+00 +11 6.560000e-03 5.000000e+00 0.000000e+00 5.000000e+00 +12 8.560000e-03 5.000000e+00 0.000000e+00 5.000000e+00 +13 1.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +14 1.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +15 1.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +16 1.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +17 1.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +18 2.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +19 2.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +20 2.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +21 2.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +22 2.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +23 3.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +24 3.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +25 3.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +26 3.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +27 3.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +28 4.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +29 4.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +30 4.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +31 4.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +32 4.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +33 5.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +34 5.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +35 5.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +36 5.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +37 5.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +38 6.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +39 6.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +40 6.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +41 6.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +42 6.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +43 7.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +44 7.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +45 7.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +46 7.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +47 7.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +48 8.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +49 8.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +50 8.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +51 8.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +52 8.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +53 9.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +54 9.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 + +Index time V(5) V(7) V(9) +-------------------------------------------------------------------------------- +55 9.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +56 9.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +57 9.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +58 1.000000e-01 5.000000e+00 0.000000e+00 5.000000e+00 + +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:29:51 2015 +Transient Analysis Tue Jun 30 14:47:07 2015 +-------------------------------------------------------------------------------- +Index time V(10) V(11) +-------------------------------------------------------------------------------- +0 0.000000e+00 5.000000e+00 0.000000e+00 +1 1.000000e-05 5.000000e+00 0.000000e+00 +2 2.000000e-05 5.000000e+00 0.000000e+00 +3 4.000000e-05 5.000000e+00 0.000000e+00 +4 8.000000e-05 5.000000e+00 0.000000e+00 +5 1.600000e-04 5.000000e+00 0.000000e+00 +6 3.200000e-04 5.000000e+00 0.000000e+00 +7 6.400000e-04 5.000000e+00 0.000000e+00 +8 1.280000e-03 5.000000e+00 0.000000e+00 +9 2.560000e-03 5.000000e+00 0.000000e+00 +10 4.560000e-03 5.000000e+00 0.000000e+00 +11 6.560000e-03 5.000000e+00 0.000000e+00 +12 8.560000e-03 5.000000e+00 0.000000e+00 +13 1.056000e-02 5.000000e+00 0.000000e+00 +14 1.256000e-02 5.000000e+00 0.000000e+00 +15 1.456000e-02 5.000000e+00 0.000000e+00 +16 1.656000e-02 5.000000e+00 0.000000e+00 +17 1.856000e-02 5.000000e+00 0.000000e+00 +18 2.056000e-02 5.000000e+00 0.000000e+00 +19 2.256000e-02 5.000000e+00 0.000000e+00 +20 2.456000e-02 5.000000e+00 0.000000e+00 +21 2.656000e-02 5.000000e+00 0.000000e+00 +22 2.856000e-02 5.000000e+00 0.000000e+00 +23 3.056000e-02 5.000000e+00 0.000000e+00 +24 3.256000e-02 5.000000e+00 0.000000e+00 +25 3.456000e-02 5.000000e+00 0.000000e+00 +26 3.656000e-02 5.000000e+00 0.000000e+00 +27 3.856000e-02 5.000000e+00 0.000000e+00 +28 4.056000e-02 5.000000e+00 0.000000e+00 +29 4.256000e-02 5.000000e+00 0.000000e+00 +30 4.456000e-02 5.000000e+00 0.000000e+00 +31 4.656000e-02 5.000000e+00 0.000000e+00 +32 4.856000e-02 5.000000e+00 0.000000e+00 +33 5.056000e-02 5.000000e+00 0.000000e+00 +34 5.256000e-02 5.000000e+00 0.000000e+00 +35 5.456000e-02 5.000000e+00 0.000000e+00 +36 5.656000e-02 5.000000e+00 0.000000e+00 +37 5.856000e-02 5.000000e+00 0.000000e+00 +38 6.056000e-02 5.000000e+00 0.000000e+00 +39 6.256000e-02 5.000000e+00 0.000000e+00 +40 6.456000e-02 5.000000e+00 0.000000e+00 +41 6.656000e-02 5.000000e+00 0.000000e+00 +42 6.856000e-02 5.000000e+00 0.000000e+00 +43 7.056000e-02 5.000000e+00 0.000000e+00 +44 7.256000e-02 5.000000e+00 0.000000e+00 +45 7.456000e-02 5.000000e+00 0.000000e+00 +46 7.656000e-02 5.000000e+00 0.000000e+00 +47 7.856000e-02 5.000000e+00 0.000000e+00 +48 8.056000e-02 5.000000e+00 0.000000e+00 +49 8.256000e-02 5.000000e+00 0.000000e+00 +50 8.456000e-02 5.000000e+00 0.000000e+00 +51 8.656000e-02 5.000000e+00 0.000000e+00 +52 8.856000e-02 5.000000e+00 0.000000e+00 +53 9.056000e-02 5.000000e+00 0.000000e+00 +54 9.256000e-02 5.000000e+00 0.000000e+00 + +Index time V(10) V(11) +-------------------------------------------------------------------------------- +55 9.456000e-02 5.000000e+00 0.000000e+00 +56 9.656000e-02 5.000000e+00 0.000000e+00 +57 9.856000e-02 5.000000e+00 0.000000e+00 +58 1.000000e-01 5.000000e+00 0.000000e+00 |