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| author | VaradhaCodes | 2025-05-29 15:46:33 +0530 |
|---|---|---|
| committer | VaradhaCodes | 2025-05-29 15:46:33 +0530 |
| commit | 76b3d415476c5c07c58dba74af8c328405746c00 (patch) | |
| tree | 4f652fa68f72177596c9ad37c06090662557e1fe /Examples/Dualtimer/analysis | |
| parent | d186a100dffba2477342fa44f885ea541c1284bb (diff) | |
| download | eSim-76b3d415476c5c07c58dba74af8c328405746c00.tar.gz eSim-76b3d415476c5c07c58dba74af8c328405746c00.tar.bz2 eSim-76b3d415476c5c07c58dba74af8c328405746c00.zip | |
Fix: Handle single-line port declarations in Verilog modules (Closes #270)
Diffstat (limited to 'Examples/Dualtimer/analysis')
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