remove temporary files

13 files changed, 0 insertions, 668 deletions

diff --git a/Examples/Diac_Triac/.triac.s.swp b/Examples/Diac_Triac/.triac.s.swp
deleted file mode 100644
index 1a4c2d0e..00000000
--- a/Examples/Diac_Triac/.triac.s.swp
+++ /dev/null
diff --git a/Examples/Diac_Triac/.triac.sub.swp b/Examples/Diac_Triac/.triac.sub.swp
deleted file mode 100644
index 521ce758..00000000
--- a/Examples/Diac_Triac/.triac.sub.swp
+++ /dev/null
diff --git a/Examples/Diac_Triac/diac-cache.lib b/Examples/Diac_Triac/diac-cache.lib
deleted file mode 100644
index b15fdeec..00000000
--- a/Examples/Diac_Triac/diac-cache.lib
+++ /dev/null
@@ -1,67 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# GND
-#
-DEF GND #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 -250 50 H I C CNN
-F1 "GND" 0 -150 50 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-P 6 0 1 0  0 0  0 -50  50 -50  0 -100  -50 -50  0 -50 N
-X GND 1 0 0 0 D 50 50 1 1 W N
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 8 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-ENDDRAW
-ENDDEF
-#
-# PWR_FLAG
-#
-DEF PWR_FLAG #FLG 0 0 N N 1 F P
-F0 "#FLG" 0 95 50 H I C CNN
-F1 "PWR_FLAG" 0 180 50 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-X pwr 1 0 0 0 U 20 20 0 0 w
-P 6 0 1 0  0 0  0 50  -75 100  0 150  75 100  0 50 N
-ENDDRAW
-ENDDEF
-#
-# aswitch
-#
-DEF aswitch U 0 40 Y Y 1 F N
-F0 "U" 450 300 60 H V C CNN
-F1 "aswitch" 450 200 60 H V C CNN
-F2 "" 450 100 60 H V C CNN
-F3 "" 450 100 60 H V C CNN
-DRAW
-S 200 250 650 100 0 1 0 N
-X ~ 2 0 150 200 R 50 50 1 1 O
-X ~ 3 850 150 200 L 50 50 1 1 O
-X ~ 1_IN 450 -100 200 U 50 20 1 1 I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/Examples/Diac_Triac/diac.bak b/Examples/Diac_Triac/diac.bak
deleted file mode 100644
index 16009984..00000000
--- a/Examples/Diac_Triac/diac.bak
+++ /dev/null
@@ -1,138 +0,0 @@
-EESchema Schematic File Version 2  date 09/22/14 16:36:31

-LIBS:power

-LIBS:device

-LIBS:transistors

-LIBS:conn

-LIBS:linear

-LIBS:regul

-LIBS:74xx

-LIBS:cmos4000

-LIBS:adc-dac

-LIBS:memory

-LIBS:xilinx

-LIBS:special

-LIBS:microcontrollers

-LIBS:dsp

-LIBS:microchip

-LIBS:analog_switches

-LIBS:motorola

-LIBS:texas

-LIBS:intel

-LIBS:audio

-LIBS:interface

-LIBS:digital-audio

-LIBS:philips

-LIBS:display

-LIBS:cypress

-LIBS:siliconi

-LIBS:opto

-LIBS:atmel

-LIBS:contrib

-LIBS:valves

-LIBS:analogSpice

-LIBS:analogXSpice

-LIBS:convergenceAidSpice

-LIBS:converterSpice

-LIBS:digitalSpice

-LIBS:digitalXSpice

-LIBS:linearSpice

-LIBS:measurementSpice

-LIBS:portSpice

-LIBS:sourcesSpice

-LIBS:diac-cache

-EELAYER 25  0

-EELAYER END

-$Descr A4 11700 8267

-encoding utf-8

-Sheet 1 1

-Title ""

-Date "22 sep 2014"

-Rev ""

-Comp ""

-Comment1 ""

-Comment2 ""

-Comment3 ""

-Comment4 ""

-$EndDescr

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-Wire Wire Line

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-Wire Wire Line

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-Wire Wire Line

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-Connection ~ 4600 3400

-Wire Wire Line

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-Wire Wire Line

-	4600 2750 4150 2750

-Wire Wire Line

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-Wire Wire Line

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-Connection ~ 4150 3450

-Wire Wire Line

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-Wire Wire Line

-	4900 3750 4900 3600

-Wire Wire Line

-	4150 4100 4150 4300

-$Comp

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-U 1 1 5417D647

-P 4150 4300

-F 0 "#FLG01" H 4150 4570 30  0001 C CNN

-F 1 "PWR_FLAG" H 4150 4530 30  0000 C CNN

-	1    4150 4300

-	0    1    1    0   

-$EndComp

-$Comp

-L PORT U3

-U 2 1 5417D62C

-P 5450 3400

-F 0 "U3" H 5450 3350 30  0000 C CNN

-F 1 "PORT" H 5450 3400 30  0000 C CNN

-	2    5450 3400

-	-1   0    0    1   

-$EndComp

-$Comp

-L PORT U3

-U 1 1 5417D624

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-F 1 "PORT" H 4150 2500 30  0000 C CNN

-	1    4150 2500

-	0    1    1    0   

-$EndComp

-$Comp

-L GND #PWR02

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-F 0 "#PWR02" H 4150 4300 30  0001 C CNN

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-$EndComp

-$Comp

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diff --git a/Examples/Diac_Triac/diac.cir.ckt b/Examples/Diac_Triac/diac.cir.ckt
deleted file mode 100644
index e89f9cfb..00000000
--- a/Examples/Diac_Triac/diac.cir.ckt
+++ /dev/null
@@ -1,9 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: 09/22/14 16:36:23

-

-u3  1 2 port

-* Analog Switch analogswitch

-* Analog Switch analogswitch

-a1 1 (1 2) u2

-.model u2 aswitch(cntl_on=-25 cntl_off=-0.1 r_on=0.0125 r_off=1000000)

-a2 1 (1 2) u1

-.model u1 aswitch(cntl_on=25 cntl_off=0.1 r_on=0.0125 r_off=1000000)

diff --git a/Examples/Diac_Triac/diac.cir.out~ b/Examples/Diac_Triac/diac.cir.out~
deleted file mode 100644
index 89cc8142..00000000
--- a/Examples/Diac_Triac/diac.cir.out~
+++ /dev/null
@@ -1,24 +0,0 @@
-* /opt/esim/src/subcircuitlibrary/diac/diac.cir
-
-* u3  1 2 port
-* u1  1 1 2 aswitch
-* u2  1 1 2 aswitch
-a1 1 [1 2 ] u1
-a2 1 [1 2 ] u2
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) 
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) 
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) 
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/Examples/Diac_Triac/diac.sub~ b/Examples/Diac_Triac/diac.sub~
deleted file mode 100644
index 43c2d279..00000000
--- a/Examples/Diac_Triac/diac.sub~
+++ /dev/null
@@ -1,18 +0,0 @@
-* Subcircuit diac
-.subckt diac 1 2 
-* /opt/esim/src/subcircuitlibrary/diac/diac.cir
-* u1  1 1 2 aswitch
-* u2  1 1 2 aswitch
-a1 1 [1 2 ] u1
-a2 1 [1 2 ] u2
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 )
-* Control Statements
-
-.ends diac
\ No newline at end of file
diff --git a/Examples/Diac_Triac/diac_Previous_Values.xml b/Examples/Diac_Triac/diac_Previous_Values.xml
deleted file mode 100644
index 96df431c..00000000
--- a/Examples/Diac_Triac/diac_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u1 name="type">aswitch<field1 name="Enter Log (default=TRUE)" /><field2 name="Enter Control OFF value (default=0.0)">0.1</field2><field3 name="Enter OFF Resistance (default=1.0e12)">1000000</field3><field4 name="Enter ON Resistance (default=1.0)">0.0125</field4><field5 name="Enter Control ON value(default=1.0)">25</field5></u1><u2 name="type">aswitch<field6 name="Enter Log (default=TRUE)" /><field7 name="Enter Control OFF value (default=0.0)">-0.1</field7><field8 name="Enter OFF Resistance (default=1.0e12)">1000000</field8><field9 name="Enter ON Resistance (default=1.0)">0.0125</field9><field10 name="Enter Control ON value(default=1.0)">-25</field10></u2></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/Examples/Diac_Triac/triac.bak b/Examples/Diac_Triac/triac.bak
deleted file mode 100644
index f30533a0..00000000
--- a/Examples/Diac_Triac/triac.bak
+++ /dev/null
@@ -1,308 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
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-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
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diff --git a/Examples/Diac_Triac/triac.cir.ckt b/Examples/Diac_Triac/triac.cir.ckt
deleted file mode 100644
index 821b417b..00000000
--- a/Examples/Diac_Triac/triac.cir.ckt
+++ /dev/null
@@ -1,26 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: 09/20/14 11:23:24

-.include diode.lib

-

-u3  7 4 5 port

-* f3

-d2  3 2 diode

-v3  2 1 dc 0

-* Analog Switch analogswitch

-d1  11 7 diode

-* f2

-v2  8 10 dc 0

-* Analog Switch analogswitch

-c1  7 9 10u

-r1  7 9 1

-* f1

-v1  5 6 dc 0

-Vf3 3 7 0

-f3 7 9 Vf3 10

-Vf2 10 11 0

-f2 7 9 Vf2 10

-Vf1 6 7 0

-f1 7 9 Vf1 100

-a1 9 (1 4) u2

-.model u2 aswitch(cntl_on=-1 cntl_off=-0.1 r_on=0.0125 r_off=1000000)

-a2 9 (4 8) u1

-.model u1 aswitch(cntl_on=1 cntl_off=0.1 r_on=0.0125 r_off=1000000)

diff --git a/Examples/Diac_Triac/triac.cir.out~ b/Examples/Diac_Triac/triac.cir.out~
deleted file mode 100644
index 7bd15a7b..00000000
--- a/Examples/Diac_Triac/triac.cir.out~
+++ /dev/null
@@ -1,41 +0,0 @@
-* /opt/esim/src/subcircuitlibrary/triac/triac.cir
-
-.include PowerDiode.lib
-* u3  8 11 10 port
-* f3
-v3 7 2  dc 0
-* f2
-v2 6 3  dc 0
-c1  8 9 10u
-* f1
-v1 10 4  dc 0
-* u1  9 11 6 aswitch
-* u2  9 2 11 aswitch
-r1  8 9 1
-d1 5 8 PowerDiode
-d2 1 7 PowerDiode
-Vf3 1 8 0
-f3 8 9 Vf3 10
-Vf2 3 5 0
-f2 8 9 Vf2 10
-Vf1 4 8 0
-f1 8 9 Vf1 100
-a1 9 [11 6 ] u1
-a2 9 [2 11 ] u2
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 ) 
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 ) 
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 ) 
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/Examples/Diac_Triac/triac.sub~ b/Examples/Diac_Triac/triac.sub~
deleted file mode 100644
index ebbed05e..00000000
--- a/Examples/Diac_Triac/triac.sub~
+++ /dev/null
@@ -1,35 +0,0 @@
-* Subcircuit triac
-.subckt triac 8 11 10 
-* /opt/esim/src/subcircuitlibrary/triac/triac.cir
-.include PowerDiode.lib
-* f3
-v3 7 2  dc 0
-* f2
-v2 6 3  dc 0
-c1  8 9 10u
-* f1
-v1 10 4  dc 0
-* u1  9 11 6 aswitch
-* u2  9 2 11 aswitch
-r1  8 9 1
-d1 5 8 PowerDiode
-d2 1 7 PowerDiode
-Vf3 1 8 0
-f3 8 9 Vf3 10
-Vf2 3 5 0
-f2 8 9 Vf2 10
-Vf1 4 8 0
-f1 8 9 Vf1 100
-a1 9 [11 6 ] u1
-a2 9 [2 11 ] u2
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 )
-* Control Statements
-
-.ends triac
\ No newline at end of file
diff --git a/Examples/Diac_Triac/triac_Previous_Values.xml b/Examples/Diac_Triac/triac_Previous_Values.xml
deleted file mode 100644
index 80da52b3..00000000
--- a/Examples/Diac_Triac/triac_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source><v3 name="Source type">dc<field1 name="Value">0</field1></v3><v2 name="Source type">dc<field1 name="Value">0</field1></v2><v1 name="Source type">dc<field1 name="Value">0</field1></v1></source><model><u1 name="type">aswitch<field1 name="Enter Log (default=TRUE)" /><field2 name="Enter Control OFF value (default=0.0)">0.1</field2><field3 name="Enter OFF Resistance (default=1.0e12)">1000000</field3><field4 name="Enter ON Resistance (default=1.0)">0.0125</field4><field5 name="Enter Control ON value(default=1.0)">1</field5></u1><u2 name="type">aswitch<field6 name="Enter Log (default=TRUE)" /><field7 name="Enter Control OFF value (default=0.0)">-0.1</field7><field8 name="Enter OFF Resistance (default=1.0e12)">1000000</field8><field9 name="Enter ON Resistance (default=1.0)">0.0125</field9><field10 name="Enter Control ON value(default=1.0)">-1</field10></u2></model><devicemodel><d2><field>/opt/eSim/src/deviceModelLibrary/Diode/PowerDiode.lib</field></d2><d1><field>/opt/eSim/src/deviceModelLibrary/Diode/PowerDiode.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file