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authorsaurabhb172020-03-18 18:27:02 +0530
committersaurabhb172020-03-18 18:27:02 +0530
commit3aa3c9f7f6b7e30c89dc8a83515044bb74854064 (patch)
tree707ef78111e714b4826b781288821fb53333daed /Examples/Analysis_Of_Digital_IC/4073_test/4073.cir
parent50cc0a9c65834db636c502cde6548f9e3971600c (diff)
downloadeSim-3aa3c9f7f6b7e30c89dc8a83515044bb74854064.tar.gz
eSim-3aa3c9f7f6b7e30c89dc8a83515044bb74854064.tar.bz2
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fixes in Analysis of Digital ICs directory
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+* C:\Users\malli\eSim\src\SubcircuitLibrary\4073\4073.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:41:15
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U1-Pad9_ 3_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT
+X3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ 3_and
+X2 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad10_ 3_and
+
+.end