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authorsaurabhb172020-03-18 18:27:02 +0530
committersaurabhb172020-03-18 18:27:02 +0530
commit3aa3c9f7f6b7e30c89dc8a83515044bb74854064 (patch)
tree707ef78111e714b4826b781288821fb53333daed /Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir~fellowship2019-python3
parent50cc0a9c65834db636c502cde6548f9e3971600c (diff)
downloadeSim-3aa3c9f7f6b7e30c89dc8a83515044bb74854064.tar.gz
eSim-3aa3c9f7f6b7e30c89dc8a83515044bb74854064.tar.bz2
eSim-3aa3c9f7f6b7e30c89dc8a83515044bb74854064.zip
fixes in Analysis of Digital ICs directory
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-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
-U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
-
-.end