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authorsaurabhb172020-03-11 14:59:48 +0530
committersaurabhb172020-03-11 14:59:48 +0530
commitdc61eab5251234f02c0377ea328b929340b3604c (patch)
treef1bf080150f8e19788b2dc56eeb10021a44b2c2f /Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir
parent6ebbcc31ea0ce5c78c94718e2e46d87592c5d22b (diff)
downloadeSim-dc61eab5251234f02c0377ea328b929340b3604c.tar.gz
eSim-dc61eab5251234f02c0377ea328b929340b3604c.tar.bz2
eSim-dc61eab5251234f02c0377ea328b929340b3604c.zip
cleanup part2
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diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir
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-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
-U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
-
-.end