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authorsaurabhb172020-03-11 14:59:48 +0530
committersaurabhb172020-03-11 14:59:48 +0530
commitdc61eab5251234f02c0377ea328b929340b3604c (patch)
treef1bf080150f8e19788b2dc56eeb10021a44b2c2f /Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub~fellowship2019-python3
parent6ebbcc31ea0ce5c78c94718e2e46d87592c5d22b (diff)
downloadeSim-dc61eab5251234f02c0377ea328b929340b3604c.tar.gz
eSim-dc61eab5251234f02c0377ea328b929340b3604c.tar.bz2
eSim-dc61eab5251234f02c0377ea328b929340b3604c.zip
cleanup part2
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+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and \ No newline at end of file