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authorsaurabhb172020-03-18 18:27:02 +0530
committersaurabhb172020-03-18 18:27:02 +0530
commit3aa3c9f7f6b7e30c89dc8a83515044bb74854064 (patch)
tree707ef78111e714b4826b781288821fb53333daed /Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out~fellowship2019-python3
parent50cc0a9c65834db636c502cde6548f9e3971600c (diff)
downloadeSim-3aa3c9f7f6b7e30c89dc8a83515044bb74854064.tar.gz
eSim-3aa3c9f7f6b7e30c89dc8a83515044bb74854064.tar.bz2
eSim-3aa3c9f7f6b7e30c89dc8a83515044bb74854064.zip
fixes in Analysis of Digital ICs directory
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-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end