diff options
| author | Rahul P | 2020-03-04 17:01:11 +0530 |
|---|---|---|
| committer | GitHub | 2020-03-04 17:01:11 +0530 |
| commit | 8ffe81b36caa259151978de0434e4e0c5c32d217 (patch) | |
| tree | 32202454d13dfabbf6556e98987f2a9632619ea9 /Examples/Analysis_Of_Digital_IC/4002_test | |
| parent | e40317e709c220176fc5b7edf23d4434504335b0 (diff) | |
| parent | 13f3bcfda9416624cebbf5705de398e8efcad344 (diff) | |
| download | eSim-8ffe81b36caa259151978de0434e4e0c5c32d217.tar.gz eSim-8ffe81b36caa259151978de0434e4e0c5c32d217.tar.bz2 eSim-8ffe81b36caa259151978de0434e4e0c5c32d217.zip | |
Merge pull request #132 from rahulp13/master
major changes
Diffstat (limited to 'Examples/Analysis_Of_Digital_IC/4002_test')
15 files changed, 1434 insertions, 0 deletions
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002-cache.lib b/Examples/Analysis_Of_Digital_IC/4002_test/4002-cache.lib new file mode 100644 index 00000000..dd565db9 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002-cache.lib @@ -0,0 +1,82 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002.cir b/Examples/Analysis_Of_Digital_IC/4002_test/4002.cir new file mode 100644 index 00000000..36ad9450 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002.cir @@ -0,0 +1,17 @@ +* C:\Users\Bhargav\eSim\src\SubcircuitLibrary\4002\4002.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 09:36:54
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_or
+U3 Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
+U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad1_ d_nor
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT
+U4 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_or
+U5 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_or
+U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U1-Pad13_ d_nor
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002.cir.out b/Examples/Analysis_Of_Digital_IC/4002_test/4002.cir.out new file mode 100644 index 00000000..ca055749 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002.cir.out @@ -0,0 +1,36 @@ +* c:\users\bhargav\esim\src\subcircuitlibrary\4002\4002.cir
+
+* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad5_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_nor
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or
+* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or
+* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_nor
+a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6
+a4 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a5 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002.pro b/Examples/Analysis_Of_Digital_IC/4002_test/4002.pro new file mode 100644 index 00000000..e7859256 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002.pro @@ -0,0 +1,44 @@ +update=05/31/19 09:35:41
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog
+LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices
+LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital
+LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid
+LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous
+LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot
+LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power
+LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources
+LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt
+LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User
+LibName11=power
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002.sch b/Examples/Analysis_Of_Digital_IC/4002_test/4002.sch new file mode 100644 index 00000000..38f453cd --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002.sch @@ -0,0 +1,315 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U2
+U 1 1 5CEE059A
+P 4750 2900
+F 0 "U2" H 4750 2900 60 0000 C CNN
+F 1 "d_or" H 4750 3000 60 0000 C CNN
+F 2 "" H 4750 2900 60 0000 C CNN
+F 3 "" H 4750 2900 60 0000 C CNN
+ 1 4750 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U3
+U 1 1 5CEE0629
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+F 1 "d_or" H 4750 3550 60 0000 C CNN
+F 2 "" H 4750 3450 60 0000 C CNN
+F 3 "" H 4750 3450 60 0000 C CNN
+ 1 4750 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U6
+U 1 1 5CEE0663
+P 6000 3100
+F 0 "U6" H 6000 3100 60 0000 C CNN
+F 1 "d_nor" H 6050 3200 60 0000 C CNN
+F 2 "" H 6000 3100 60 0000 C CNN
+F 3 "" H 6000 3100 60 0000 C CNN
+ 1 6000 3100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5200 2850 5400 2850
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+ 5400 2850 5400 3000
+Wire Wire Line
+ 5400 3000 5550 3000
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 5650 5800 6050 5800
+Wire Wire Line
+ 5650 6000 6050 6000
+NoConn ~ 5650 5350
+NoConn ~ 5650 5550
+NoConn ~ 5650 5800
+NoConn ~ 5650 6000
+$Comp
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+F 3 "" H 3850 2800 60 0000 C CNN
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+ 1 0 0 -1
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+$Comp
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+U 3 1 5CEE22EE
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+ 1 0 0 -1
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+F 2 "" H 3900 3250 60 0000 C CNN
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+ 1 0 0 -1
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+$Comp
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+F 1 "PORT" H 3900 3550 30 0000 C CNN
+F 2 "" H 3900 3550 60 0000 C CNN
+F 3 "" H 3900 3550 60 0000 C CNN
+ 4 3900 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5CEE2387
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+F 0 "U1" H 7000 3150 30 0000 C CNN
+F 1 "PORT" H 6950 3050 30 0000 C CNN
+F 2 "" H 6950 3050 60 0000 C CNN
+F 3 "" H 6950 3050 60 0000 C CNN
+ 1 6950 3050
+ -1 0 0 1
+$EndComp
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+F 0 "U4" H 4900 4100 60 0000 C CNN
+F 1 "d_or" H 4900 4200 60 0000 C CNN
+F 2 "" H 4900 4100 60 0000 C CNN
+F 3 "" H 4900 4100 60 0000 C CNN
+ 1 4900 4100
+ 1 0 0 -1
+$EndComp
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+L d_or U5
+U 1 1 5CEE4EDD
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+F 2 "" H 4900 4650 60 0000 C CNN
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+ 1 4900 4650
+ 1 0 0 -1
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+$Comp
+L d_nor U7
+U 1 1 5CEE4EE3
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+F 0 "U7" H 6150 4300 60 0000 C CNN
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+F 2 "" H 6150 4300 60 0000 C CNN
+F 3 "" H 6150 4300 60 0000 C CNN
+ 1 6150 4300
+ 1 0 0 -1
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+Wire Wire Line
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+F 2 "" H 4000 4000 60 0000 C CNN
+F 3 "" H 4000 4000 60 0000 C CNN
+ 9 4000 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5CEE4EF5
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+F 2 "" H 4050 4250 60 0000 C CNN
+F 3 "" H 4050 4250 60 0000 C CNN
+ 10 4050 4250
+ 1 0 0 -1
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+ 11 4050 4450
+ 1 0 0 -1
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+ 12 4050 4750
+ 1 0 0 -1
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+ -1 0 0 1
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+Wire Wire Line
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+ -1 0 0 1
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+ -1 0 0 1
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+F 3 "" H 6300 5800 60 0000 C CNN
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+ -1 0 0 1
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+$Comp
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+U 14 1 5CEE52C5
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+F 0 "U1" H 6350 6100 30 0000 C CNN
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diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002.sub b/Examples/Analysis_Of_Digital_IC/4002_test/4002.sub new file mode 100644 index 00000000..522ba7ae --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002.sub @@ -0,0 +1,30 @@ +* Subcircuit 4002
+.subckt 4002 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ?
+* c:\users\bhargav\esim\src\subcircuitlibrary\4002\4002.cir
+* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad5_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_nor
+* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or
+* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or
+* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_nor
+a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6
+a4 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a5 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4002
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4002_test/4002_Previous_Values.xml new file mode 100644 index 00000000..75360e5e --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u6><u4 name="type">d_or<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u7 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-cache.lib b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-cache.lib new file mode 100644 index 00000000..53c89e01 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-cache.lib @@ -0,0 +1,140 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H V C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# IC_4002
+#
+DEF IC_4002 X 0 40 Y Y 1 F N
+F0 "X" 0 150 60 H V C CNN
+F1 "IC_4002" 0 0 60 H V C CNN
+F2 "" 50 -150 60 H V C CNN
+F3 "" 50 -150 60 H V C CNN
+DRAW
+S -250 350 250 -400 0 1 0 N
+X 1Y 1 -450 250 200 R 50 50 1 1 O
+X 1A 2 -450 150 200 R 50 50 1 1 I
+X 1B 3 -450 50 200 R 50 50 1 1 I
+X 1C 4 -450 -50 200 R 50 50 1 1 I
+X 1D 5 -450 -150 200 R 50 50 1 1 I
+X NC 6 -450 -250 200 R 50 50 1 1 I
+X GND 7 -450 -350 200 R 50 50 1 1 I
+X NC 8 450 -350 200 L 50 50 1 1 I
+X 2A 9 450 -250 200 L 50 50 1 1 I
+X 2B 10 450 -150 200 L 50 50 1 1 I
+X 2C 11 450 -50 200 L 50 50 1 1 I
+X 2D 12 450 50 200 L 50 50 1 1 I
+X 2Y 13 450 150 200 L 50 50 1 1 O
+X VCC 14 450 250 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 95 50 H I C CNN
+F1 "PWR_FLAG" 0 180 50 H V C CNN
+F2 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_4
+#
+DEF adc_bridge_4 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_4" 0 300 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 350 350 -200 0 1 0 N
+X IN1 1 -550 200 200 R 50 50 1 1 I
+X IN2 2 -550 100 200 R 50 50 1 1 I
+X IN3 3 -550 0 200 R 50 50 1 1 I
+X IN4 4 -550 -100 200 R 50 50 1 1 I
+X OUT1 5 550 200 200 L 50 50 1 1 O
+X OUT2 6 550 100 200 L 50 50 1 1 O
+X OUT3 7 550 0 200 L 50 50 1 1 O
+X OUT4 8 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_2
+#
+DEF dac_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_2" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -250 200 350 -100 0 1 0 N
+X IN1 1 -450 50 200 R 50 50 1 1 I
+X IN2 2 -450 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT4 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.cir b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.cir new file mode 100644 index 00000000..a667c576 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.cir @@ -0,0 +1,42 @@ +* C:\Users\Bhargav\eSim-Workspace\4002_test\4002_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 06:09:49
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U2-Pad1_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ ? ? ? Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ Net-_U2-Pad2_ ? IC_4002
+U1 Net-_R1-Pad2_ Net-_R2-Pad2_ Net-_R3-Pad2_ Net-_R4-Pad2_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ adc_bridge_4
+U3 Net-_R10-Pad1_ Net-_R9-Pad1_ Net-_R8-Pad1_ Net-_R7-Pad1_ Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ adc_bridge_4
+U2 Net-_U2-Pad1_ Net-_U2-Pad2_ out1 out2 dac_bridge_2
+R5 out1 GND 1k
+R6 out2 GND 1k
+U9 out1 plot_v1
+U8 out2 plot_v1
+U13 v8 plot_v1
+U10 v7 plot_v1
+U11 v6 plot_v1
+U12 v5 plot_v1
+R10 Net-_R10-Pad1_ v8 1k
+R9 Net-_R9-Pad1_ v7 1k
+R8 Net-_R8-Pad1_ v6 1k
+R7 Net-_R7-Pad1_ v5 1k
+v6 v7 GND DC
+v5 v8 GND DC
+v8 v5 GND DC
+v7 v6 GND DC
+U7 v4 plot_v1
+U4 v3 plot_v1
+U6 v2 plot_v1
+U5 v1 plot_v1
+R4 v4 Net-_R4-Pad2_ 1k
+R3 v3 Net-_R3-Pad2_ 1k
+R2 v2 Net-_R2-Pad2_ 1k
+R1 v1 Net-_R1-Pad2_ 1k
+v4 v4 GND DC
+v3 v3 GND DC
+v2 v2 GND DC
+v1 v1 GND DC
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.cir.out b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.cir.out new file mode 100644 index 00000000..2dbfc43b --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.cir.out @@ -0,0 +1,63 @@ +* c:\users\bhargav\esim-workspace\4002_test\4002_test.cir
+
+.include 4002.sub
+x1 net-_u2-pad1_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ? ? ? net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u2-pad2_ ? 4002
+* u1 net-_r1-pad2_ net-_r2-pad2_ net-_r3-pad2_ net-_r4-pad2_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ adc_bridge_4
+* u3 net-_r10-pad1_ net-_r9-pad1_ net-_r8-pad1_ net-_r7-pad1_ net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ adc_bridge_4
+* u2 net-_u2-pad1_ net-_u2-pad2_ out1 out2 dac_bridge_2
+r5 out1 gnd 1k
+r6 out2 gnd 1k
+* u9 out1 plot_v1
+* u8 out2 plot_v1
+* u13 v8 plot_v1
+* u10 v7 plot_v1
+* u11 v6 plot_v1
+* u12 v5 plot_v1
+r10 net-_r10-pad1_ v8 1k
+r9 net-_r9-pad1_ v7 1k
+r8 net-_r8-pad1_ v6 1k
+r7 net-_r7-pad1_ v5 1k
+v6 v7 gnd dc 0
+v5 v8 gnd dc 0
+v8 v5 gnd dc 0
+v7 v6 gnd dc 5
+* u7 v4 plot_v1
+* u4 v3 plot_v1
+* u6 v2 plot_v1
+* u5 v1 plot_v1
+r4 v4 net-_r4-pad2_ 1k
+r3 v3 net-_r3-pad2_ 1k
+r2 v2 net-_r2-pad2_ 1k
+r1 v1 net-_r1-pad2_ 1k
+v4 v4 gnd dc 0
+v3 v3 gnd dc 0
+v2 v2 gnd dc 0
+v1 v1 gnd dc 0
+a1 [net-_r1-pad2_ net-_r2-pad2_ net-_r3-pad2_ net-_r4-pad2_ ] [net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] u1
+a2 [net-_r10-pad1_ net-_r9-pad1_ net-_r8-pad1_ net-_r7-pad1_ ] [net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ ] u3
+a3 [net-_u2-pad1_ net-_u2-pad2_ ] [out1 out2 ] u2
+* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
+.model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
+* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
+.model u3 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
+* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge
+.model u2 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 )
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(out1)
+plot v(out2)
+plot v(v8)
+plot v(v7)
+plot v(v6)
+plot v(v5)
+plot v(v4)
+plot v(v3)
+plot v(v2)
+plot v(v1)
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.pro b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.pro new file mode 100644 index 00000000..43701631 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.pro @@ -0,0 +1,44 @@ +update=06/01/19 05:45:01
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog
+LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices
+LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital
+LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid
+LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous
+LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot
+LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power
+LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources
+LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt
+LibName11=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.proj b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.proj new file mode 100644 index 00000000..e13b6026 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.proj @@ -0,0 +1 @@ +schematicFile 4002_test.sch
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.sch b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.sch new file mode 100644 index 00000000..1cce0878 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.sch @@ -0,0 +1,617 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
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+ 1 0 0 -1
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