CD4078B is a CMOS quad 2-input OR gate

8 files changed, 1158 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC-cache.lib b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC-cache.lib
new file mode 100644
index 00000000..57dd9d9b
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC-cache.lib
@@ -0,0 +1,138 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_8
+#
+DEF adc_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_2
+#
+DEF dac_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_2" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -250 200 350 -100 0 1 0 N
+X IN1 1 -450 50 200 R 50 50 1 1 I
+X IN2 2 -450 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT4 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.cir b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.cir
new file mode 100644
index 00000000..00f7b56f
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.cir
@@ -0,0 +1,35 @@
+* D:\FOSSEE\eSim\library\SubcircuitLibrary\CD4078B_IC\CD4078B_IC.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/18/24 16:43:14
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3  Net-_U2-Pad9_ Net-_U11-Pad1_ d_inverter		
+U4  Net-_U2-Pad10_ Net-_U11-Pad2_ d_inverter		
+U5  Net-_U2-Pad11_ Net-_U12-Pad1_ d_inverter		
+U6  Net-_U2-Pad12_ Net-_U12-Pad2_ d_inverter		
+U7  Net-_U2-Pad13_ Net-_U13-Pad1_ d_inverter		
+U8  Net-_U2-Pad14_ Net-_U13-Pad2_ d_inverter		
+U9  Net-_U2-Pad15_ Net-_U14-Pad1_ d_inverter		
+U10  Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter		
+U21  Net-_U19-Pad3_ Net-_U20-Pad3_ Net-_U21-Pad3_ d_nor		
+U22  Net-_U21-Pad3_ Net-_U22-Pad2_ d_inverter		
+U24  Net-_U22-Pad2_ Net-_U24-Pad2_ d_inverter		
+U23  Net-_U21-Pad3_ Net-_U23-Pad2_ d_inverter		
+U25  Net-_U24-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad10_ Net-_U1-Pad9_ dac_bridge_2		
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U10-Pad1_ adc_bridge_8		
+U11  Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_nand		
+U12  Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_nand		
+U15  Net-_U11-Pad3_ Net-_U11-Pad3_ Net-_U15-Pad3_ d_nand		
+U16  Net-_U12-Pad3_ Net-_U12-Pad3_ Net-_U16-Pad3_ d_nand		
+U19  Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U19-Pad3_ d_nand		
+U13  Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_nand		
+U14  Net-_U14-Pad1_ Net-_U10-Pad2_ Net-_U14-Pad3_ d_nand		
+U17  Net-_U13-Pad3_ Net-_U13-Pad3_ Net-_U17-Pad3_ d_nand		
+U18  Net-_U14-Pad3_ Net-_U14-Pad3_ Net-_U18-Pad3_ d_nand		
+U20  Net-_U17-Pad3_ Net-_U18-Pad3_ Net-_U20-Pad3_ d_nand		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.cir.out b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.cir.out
new file mode 100644
index 00000000..30c56474
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.cir.out
@@ -0,0 +1,108 @@
+* d:\fossee\esim\library\subcircuitlibrary\cd4078b_ic\cd4078b_ic.cir
+
+* u3  net-_u2-pad9_ net-_u11-pad1_ d_inverter
+* u4  net-_u2-pad10_ net-_u11-pad2_ d_inverter
+* u5  net-_u2-pad11_ net-_u12-pad1_ d_inverter
+* u6  net-_u2-pad12_ net-_u12-pad2_ d_inverter
+* u7  net-_u2-pad13_ net-_u13-pad1_ d_inverter
+* u8  net-_u2-pad14_ net-_u13-pad2_ d_inverter
+* u9  net-_u2-pad15_ net-_u14-pad1_ d_inverter
+* u10  net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u21  net-_u19-pad3_ net-_u20-pad3_ net-_u21-pad3_ d_nor
+* u22  net-_u21-pad3_ net-_u22-pad2_ d_inverter
+* u24  net-_u22-pad2_ net-_u24-pad2_ d_inverter
+* u23  net-_u21-pad3_ net-_u23-pad2_ d_inverter
+* u25  net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad10_ net-_u1-pad9_ dac_bridge_2
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ adc_bridge_8
+* u11  net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand
+* u12  net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nand
+* u15  net-_u11-pad3_ net-_u11-pad3_ net-_u15-pad3_ d_nand
+* u16  net-_u12-pad3_ net-_u12-pad3_ net-_u16-pad3_ d_nand
+* u19  net-_u15-pad3_ net-_u16-pad3_ net-_u19-pad3_ d_nand
+* u13  net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nand
+* u14  net-_u14-pad1_ net-_u10-pad2_ net-_u14-pad3_ d_nand
+* u17  net-_u13-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nand
+* u18  net-_u14-pad3_ net-_u14-pad3_ net-_u18-pad3_ d_nand
+* u20  net-_u17-pad3_ net-_u18-pad3_ net-_u20-pad3_ d_nand
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ port
+a1 net-_u2-pad9_ net-_u11-pad1_ u3
+a2 net-_u2-pad10_ net-_u11-pad2_ u4
+a3 net-_u2-pad11_ net-_u12-pad1_ u5
+a4 net-_u2-pad12_ net-_u12-pad2_ u6
+a5 net-_u2-pad13_ net-_u13-pad1_ u7
+a6 net-_u2-pad14_ net-_u13-pad2_ u8
+a7 net-_u2-pad15_ net-_u14-pad1_ u9
+a8 net-_u10-pad1_ net-_u10-pad2_ u10
+a9 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u21-pad3_ u21
+a10 net-_u21-pad3_ net-_u22-pad2_ u22
+a11 net-_u22-pad2_ net-_u24-pad2_ u24
+a12 net-_u21-pad3_ net-_u23-pad2_ u23
+a13 [net-_u24-pad2_ net-_u23-pad2_ ] [net-_u1-pad10_ net-_u1-pad9_ ] u25
+a14 [net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] [net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ ] u2
+a15 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a16 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a17 [net-_u11-pad3_ net-_u11-pad3_ ] net-_u15-pad3_ u15
+a18 [net-_u12-pad3_ net-_u12-pad3_ ] net-_u16-pad3_ u16
+a19 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u19-pad3_ u19
+a20 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a21 [net-_u14-pad1_ net-_u10-pad2_ ] net-_u14-pad3_ u14
+a22 [net-_u13-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17
+a23 [net-_u14-pad3_ net-_u14-pad3_ ] net-_u18-pad3_ u18
+a24 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u20-pad3_ u20
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u21 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_2, NgSpice Name: dac_bridge
+.model u25 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_8, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u20 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0.01e-03 100e-03 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.pro b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.sch b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.sch
new file mode 100644
index 00000000..9436e506
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.sch
@@ -0,0 +1,700 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:CD4078B_IC-cache
+EELAYER 25 0
+EELAYER END
+$Descr User 23622 19685
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_inverter U3
+U 1 1 66716575
+P 7850 6350
+F 0 "U3" H 7850 6250 60  0000 C CNN
+F 1 "d_inverter" H 7850 6500 60  0000 C CNN
+F 2 "" H 7900 6300 60  0000 C CNN
+F 3 "" H 7900 6300 60  0000 C CNN
+	1    7850 6350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 66716576
+P 7850 6850
+F 0 "U4" H 7850 6750 60  0000 C CNN
+F 1 "d_inverter" H 7850 7000 60  0000 C CNN
+F 2 "" H 7900 6800 60  0000 C CNN
+F 3 "" H 7900 6800 60  0000 C CNN
+	1    7850 6850
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U5
+U 1 1 66716577
+P 7850 7350
+F 0 "U5" H 7850 7250 60  0000 C CNN
+F 1 "d_inverter" H 7850 7500 60  0000 C CNN
+F 2 "" H 7900 7300 60  0000 C CNN
+F 3 "" H 7900 7300 60  0000 C CNN
+	1    7850 7350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 66716578
+P 7850 7950
+F 0 "U6" H 7850 7850 60  0000 C CNN
+F 1 "d_inverter" H 7850 8100 60  0000 C CNN
+F 2 "" H 7900 7900 60  0000 C CNN
+F 3 "" H 7900 7900 60  0000 C CNN
+	1    7850 7950
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U7
+U 1 1 66716579
+P 7850 8750
+F 0 "U7" H 7850 8650 60  0000 C CNN
+F 1 "d_inverter" H 7850 8900 60  0000 C CNN
+F 2 "" H 7900 8700 60  0000 C CNN
+F 3 "" H 7900 8700 60  0000 C CNN
+	1    7850 8750
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U8
+U 1 1 6671657A
+P 7850 9250
+F 0 "U8" H 7850 9150 60  0000 C CNN
+F 1 "d_inverter" H 7850 9400 60  0000 C CNN
+F 2 "" H 7900 9200 60  0000 C CNN
+F 3 "" H 7900 9200 60  0000 C CNN
+	1    7850 9250
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U9
+U 1 1 6671657B
+P 7850 9750
+F 0 "U9" H 7850 9650 60  0000 C CNN
+F 1 "d_inverter" H 7850 9900 60  0000 C CNN
+F 2 "" H 7900 9700 60  0000 C CNN
+F 3 "" H 7900 9700 60  0000 C CNN
+	1    7850 9750
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U10
+U 1 1 6671657C
+P 7850 10350
+F 0 "U10" H 7850 10250 60  0000 C CNN
+F 1 "d_inverter" H 7850 10500 60  0000 C CNN
+F 2 "" H 7900 10300 60  0000 C CNN
+F 3 "" H 7900 10300 60  0000 C CNN
+	1    7850 10350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U21
+U 1 1 6671657D
+P 14350 8200
+F 0 "U21" H 14350 8200 60  0000 C CNN
+F 1 "d_nor" H 14400 8300 60  0000 C CNN
+F 2 "" H 14350 8200 60  0000 C CNN
+F 3 "" H 14350 8200 60  0000 C CNN
+	1    14350 8200
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U22
+U 1 1 6671657E
+P 15350 8150
+F 0 "U22" H 15350 8050 60  0000 C CNN
+F 1 "d_inverter" H 15350 8300 60  0000 C CNN
+F 2 "" H 15400 8100 60  0000 C CNN
+F 3 "" H 15400 8100 60  0000 C CNN
+	1    15350 8150
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U24
+U 1 1 6671657F
+P 16150 8150
+F 0 "U24" H 16150 8050 60  0000 C CNN
+F 1 "d_inverter" H 16150 8300 60  0000 C CNN
+F 2 "" H 16200 8100 60  0000 C CNN
+F 3 "" H 16200 8100 60  0000 C CNN
+	1    16150 8150
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U23
+U 1 1 66716580
+P 15450 8850
+F 0 "U23" H 15450 8750 60  0000 C CNN
+F 1 "d_inverter" H 15450 9000 60  0000 C CNN
+F 2 "" H 15500 8800 60  0000 C CNN
+F 3 "" H 15500 8800 60  0000 C CNN
+	1    15450 8850
+	1    0    0    -1  
+$EndComp
+$Comp
+L dac_bridge_2 U25
+U 1 1 66716581
+P 17350 8350
+F 0 "U25" H 17350 8350 60  0000 C CNN
+F 1 "dac_bridge_2" H 17400 8500 60  0000 C CNN
+F 2 "" H 17350 8350 60  0000 C CNN
+F 3 "" H 17350 8350 60  0000 C CNN
+	1    17350 8350
+	1    0    0    -1  
+$EndComp
+$Comp
+L adc_bridge_8 U2
+U 1 1 66716584
+P 5500 8050
+F 0 "U2" H 5500 8050 60  0000 C CNN
+F 1 "adc_bridge_8" H 5500 8200 60  0000 C CNN
+F 2 "" H 5500 8050 60  0000 C CNN
+F 3 "" H 5500 8050 60  0000 C CNN
+	1    5500 8050
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	8150 6350 8800 6350
+Wire Wire Line
+	8800 6350 8800 6950
+Wire Wire Line
+	8800 6950 9100 6950
+Wire Wire Line
+	8150 6850 8700 6850
+Wire Wire Line
+	8700 6850 8700 7050
+Wire Wire Line
+	8700 7050 9250 7050
+Wire Wire Line
+	8150 7350 8700 7350
+Wire Wire Line
+	8700 7350 8700 7150
+Wire Wire Line
+	8700 7150 9700 7150
+Wire Wire Line
+	8150 7950 8800 7950
+Wire Wire Line
+	8800 7950 8800 7250
+Wire Wire Line
+	8800 7250 9600 7250
+Wire Wire Line
+	8150 8750 8750 8750
+Wire Wire Line
+	8750 8750 8750 9250
+Wire Wire Line
+	8750 9250 9150 9250
+Wire Wire Line
+	8150 9250 8650 9250
+Wire Wire Line
+	8650 9250 8650 9350
+Wire Wire Line
+	8650 9350 9300 9350
+Wire Wire Line
+	8150 9750 8650 9750
+Wire Wire Line
+	8650 9750 8650 9450
+Wire Wire Line
+	8650 9450 9350 9450
+Wire Wire Line
+	8150 10350 8750 10350
+Wire Wire Line
+	8750 10350 8750 9550
+Wire Wire Line
+	8750 9550 9300 9550
+Wire Wire Line
+	13700 8200 13900 8200
+Wire Wire Line
+	15050 8150 14800 8150
+Wire Wire Line
+	15650 8150 15850 8150
+Wire Wire Line
+	15150 8850 14950 8850
+Wire Wire Line
+	14950 8850 14950 8150
+Connection ~ 14950 8150
+Wire Wire Line
+	16450 8150 16800 8150
+Wire Wire Line
+	16800 8150 16800 8300
+Wire Wire Line
+	16800 8300 16900 8300
+Wire Wire Line
+	15750 8850 16750 8850
+Wire Wire Line
+	16750 8850 16750 8400
+Wire Wire Line
+	16750 8400 16900 8400
+Wire Wire Line
+	6050 8000 6800 8000
+Wire Wire Line
+	6800 8000 6800 6350
+Wire Wire Line
+	6800 6350 7550 6350
+Wire Wire Line
+	7550 6850 6900 6850
+Wire Wire Line
+	6900 6850 6900 8100
+Wire Wire Line
+	6900 8100 6050 8100
+Wire Wire Line
+	6050 8200 7150 8200
+Wire Wire Line
+	7150 8200 7150 7350
+Wire Wire Line
+	7150 7350 7550 7350
+Wire Wire Line
+	7550 7950 7250 7950
+Wire Wire Line
+	7250 7950 7250 8300
+Wire Wire Line
+	7250 8300 6050 8300
+Wire Wire Line
+	6050 8400 7300 8400
+Wire Wire Line
+	7300 8400 7300 8750
+Wire Wire Line
+	7300 8750 7550 8750
+Wire Wire Line
+	6050 8500 7200 8500
+Wire Wire Line
+	7200 8500 7200 9250
+Wire Wire Line
+	7200 9250 7550 9250
+Wire Wire Line
+	6050 8600 7050 8600
+Wire Wire Line
+	7050 8600 7050 9750
+Wire Wire Line
+	7050 9750 7550 9750
+Wire Wire Line
+	6050 8700 6950 8700
+Wire Wire Line
+	6950 8700 6950 10350
+Wire Wire Line
+	6950 10350 7550 10350
+$Comp
+L d_nand U11
+U 1 1 6671659D
+P 10250 7000
+F 0 "U11" H 10250 7000 60  0000 C CNN
+F 1 "d_nand" H 10300 7100 60  0000 C CNN
+F 2 "" H 10250 7000 60  0000 C CNN
+F 3 "" H 10250 7000 60  0000 C CNN
+	1    10250 7000
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nand U12
+U 1 1 6671659E
+P 10250 7500
+F 0 "U12" H 10250 7500 60  0000 C CNN
+F 1 "d_nand" H 10300 7600 60  0000 C CNN
+F 2 "" H 10250 7500 60  0000 C CNN
+F 3 "" H 10250 7500 60  0000 C CNN
+	1    10250 7500
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nand U15
+U 1 1 6671659F
+P 11550 7000
+F 0 "U15" H 11550 7000 60  0000 C CNN
+F 1 "d_nand" H 11600 7100 60  0000 C CNN
+F 2 "" H 11550 7000 60  0000 C CNN
+F 3 "" H 11550 7000 60  0000 C CNN
+	1    11550 7000
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nand U16
+U 1 1 667165A0
+P 11550 7500
+F 0 "U16" H 11550 7500 60  0000 C CNN
+F 1 "d_nand" H 11600 7600 60  0000 C CNN
+F 2 "" H 11550 7500 60  0000 C CNN
+F 3 "" H 11550 7500 60  0000 C CNN
+	1    11550 7500
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nand U19
+U 1 1 667165A1
+P 12750 7200
+F 0 "U19" H 12750 7200 60  0000 C CNN
+F 1 "d_nand" H 12800 7300 60  0000 C CNN
+F 2 "" H 12750 7200 60  0000 C CNN
+F 3 "" H 12750 7200 60  0000 C CNN
+	1    12750 7200
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	11100 6900 11000 6900
+Wire Wire Line
+	11000 6900 11000 7000
+Wire Wire Line
+	11000 7000 11100 7000
+Wire Wire Line
+	11100 7400 11000 7400
+Wire Wire Line
+	11000 7400 11000 7500
+Wire Wire Line
+	11000 7500 11100 7500
+Wire Wire Line
+	10700 6950 11000 6950
+Connection ~ 11000 6950
+Wire Wire Line
+	10700 7450 11000 7450
+Connection ~ 11000 7450
+Wire Wire Line
+	12000 6950 12150 6950
+Wire Wire Line
+	12150 6950 12150 7100
+Wire Wire Line
+	12150 7100 12300 7100
+Wire Wire Line
+	12000 7450 12150 7450
+Wire Wire Line
+	12150 7450 12150 7200
+Wire Wire Line
+	12150 7200 12300 7200
+Wire Wire Line
+	9100 6950 9100 6900
+Wire Wire Line
+	9100 6900 9800 6900
+Wire Wire Line
+	9250 7050 9250 7000
+Wire Wire Line
+	9250 7000 9800 7000
+Wire Wire Line
+	9700 7150 9700 7400
+Wire Wire Line
+	9700 7400 9800 7400
+Wire Wire Line
+	9600 7250 9600 7500
+Wire Wire Line
+	9600 7500 9800 7500
+$Comp
+L d_nand U13
+U 1 1 667165A2
+P 10250 9300
+F 0 "U13" H 10250 9300 60  0000 C CNN
+F 1 "d_nand" H 10300 9400 60  0000 C CNN
+F 2 "" H 10250 9300 60  0000 C CNN
+F 3 "" H 10250 9300 60  0000 C CNN
+	1    10250 9300
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nand U14
+U 1 1 667165A3
+P 10250 9800
+F 0 "U14" H 10250 9800 60  0000 C CNN
+F 1 "d_nand" H 10300 9900 60  0000 C CNN
+F 2 "" H 10250 9800 60  0000 C CNN
+F 3 "" H 10250 9800 60  0000 C CNN
+	1    10250 9800
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nand U17
+U 1 1 667165A4
+P 11550 9300
+F 0 "U17" H 11550 9300 60  0000 C CNN
+F 1 "d_nand" H 11600 9400 60  0000 C CNN
+F 2 "" H 11550 9300 60  0000 C CNN
+F 3 "" H 11550 9300 60  0000 C CNN
+	1    11550 9300
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nand U18
+U 1 1 667165A5
+P 11550 9800
+F 0 "U18" H 11550 9800 60  0000 C CNN
+F 1 "d_nand" H 11600 9900 60  0000 C CNN
+F 2 "" H 11550 9800 60  0000 C CNN
+F 3 "" H 11550 9800 60  0000 C CNN
+	1    11550 9800
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	11100 9200 11000 9200
+Wire Wire Line
+	11000 9200 11000 9300
+Wire Wire Line
+	11000 9300 11100 9300
+Wire Wire Line
+	11100 9700 11000 9700
+Wire Wire Line
+	11000 9700 11000 9800
+Wire Wire Line
+	11000 9800 11100 9800
+Wire Wire Line
+	10700 9250 11000 9250
+Connection ~ 11000 9250
+Wire Wire Line
+	10700 9750 11000 9750
+Connection ~ 11000 9750
+Wire Wire Line
+	9800 9200 9150 9200
+Wire Wire Line
+	9150 9200 9150 9250
+Wire Wire Line
+	9300 9350 9300 9300
+Wire Wire Line
+	9300 9300 9800 9300
+Wire Wire Line
+	9350 9450 9350 9700
+Wire Wire Line
+	9350 9700 9800 9700
+Wire Wire Line
+	9300 9550 9300 9800
+Wire Wire Line
+	9300 9800 9800 9800
+$Comp
+L d_nand U20
+U 1 1 667165A6
+P 12950 9500
+F 0 "U20" H 12950 9500 60  0000 C CNN
+F 1 "d_nand" H 13000 9600 60  0000 C CNN
+F 2 "" H 12950 9500 60  0000 C CNN
+F 3 "" H 12950 9500 60  0000 C CNN
+	1    12950 9500
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	12000 9250 12350 9250
+Wire Wire Line
+	12350 9250 12350 9400
+Wire Wire Line
+	12350 9400 12500 9400
+Wire Wire Line
+	12000 9750 12350 9750
+Wire Wire Line
+	12350 9750 12350 9500
+Wire Wire Line
+	12350 9500 12500 9500
+Wire Wire Line
+	13700 8200 13700 9450
+Wire Wire Line
+	13700 9450 13400 9450
+Wire Wire Line
+	13900 8100 13700 8100
+Wire Wire Line
+	13700 8100 13700 7150
+Wire Wire Line
+	13700 7150 13200 7150
+$Comp
+L PORT U1
+U 1 1 6671678E
+P 4050 7700
+F 0 "U1" H 4100 7800 30  0000 C CNN
+F 1 "PORT" H 4050 7700 30  0000 C CNN
+F 2 "" H 4050 7700 60  0000 C CNN
+F 3 "" H 4050 7700 60  0000 C CNN
+	1    4050 7700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 66716827
+P 4050 7900
+F 0 "U1" H 4100 8000 30  0000 C CNN
+F 1 "PORT" H 4050 7900 30  0000 C CNN
+F 2 "" H 4050 7900 60  0000 C CNN
+F 3 "" H 4050 7900 60  0000 C CNN
+	2    4050 7900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 667168B8
+P 4050 8100
+F 0 "U1" H 4100 8200 30  0000 C CNN
+F 1 "PORT" H 4050 8100 30  0000 C CNN
+F 2 "" H 4050 8100 60  0000 C CNN
+F 3 "" H 4050 8100 60  0000 C CNN
+	3    4050 8100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6671693B
+P 4050 8300
+F 0 "U1" H 4100 8400 30  0000 C CNN
+F 1 "PORT" H 4050 8300 30  0000 C CNN
+F 2 "" H 4050 8300 60  0000 C CNN
+F 3 "" H 4050 8300 60  0000 C CNN
+	4    4050 8300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 667169A8
+P 4050 8500
+F 0 "U1" H 4100 8600 30  0000 C CNN
+F 1 "PORT" H 4050 8500 30  0000 C CNN
+F 2 "" H 4050 8500 60  0000 C CNN
+F 3 "" H 4050 8500 60  0000 C CNN
+	5    4050 8500
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 66716A2D
+P 4050 8700
+F 0 "U1" H 4100 8800 30  0000 C CNN
+F 1 "PORT" H 4050 8700 30  0000 C CNN
+F 2 "" H 4050 8700 60  0000 C CNN
+F 3 "" H 4050 8700 60  0000 C CNN
+	6    4050 8700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 7 1 66716AB0
+P 4050 8900
+F 0 "U1" H 4100 9000 30  0000 C CNN
+F 1 "PORT" H 4050 8900 30  0000 C CNN
+F 2 "" H 4050 8900 60  0000 C CNN
+F 3 "" H 4050 8900 60  0000 C CNN
+	7    4050 8900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 8 1 66716B2F
+P 4050 9100
+F 0 "U1" H 4100 9200 30  0000 C CNN
+F 1 "PORT" H 4050 9100 30  0000 C CNN
+F 2 "" H 4050 9100 60  0000 C CNN
+F 3 "" H 4050 9100 60  0000 C CNN
+	8    4050 9100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4300 7700 4800 7700
+Wire Wire Line
+	4800 7700 4800 8000
+Wire Wire Line
+	4800 8000 4900 8000
+Wire Wire Line
+	4300 7900 4750 7900
+Wire Wire Line
+	4750 7900 4750 8100
+Wire Wire Line
+	4750 8100 4900 8100
+Wire Wire Line
+	4300 8100 4650 8100
+Wire Wire Line
+	4650 8100 4650 8200
+Wire Wire Line
+	4650 8200 4900 8200
+Wire Wire Line
+	4300 8300 4900 8300
+Wire Wire Line
+	4300 8500 4750 8500
+Wire Wire Line
+	4750 8500 4750 8400
+Wire Wire Line
+	4750 8400 4900 8400
+Wire Wire Line
+	4300 8700 4800 8700
+Wire Wire Line
+	4800 8700 4800 8500
+Wire Wire Line
+	4800 8500 4900 8500
+Wire Wire Line
+	4300 8900 4850 8900
+Wire Wire Line
+	4850 8900 4850 8600
+Wire Wire Line
+	4850 8600 4900 8600
+Wire Wire Line
+	4300 9100 4900 9100
+Wire Wire Line
+	4900 9100 4900 8700
+$Comp
+L PORT U1
+U 9 1 667175F2
+P 18450 8450
+F 0 "U1" H 18500 8550 30  0000 C CNN
+F 1 "PORT" H 18450 8450 30  0000 C CNN
+F 2 "" H 18450 8450 60  0000 C CNN
+F 3 "" H 18450 8450 60  0000 C CNN
+	9    18450 8450
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6671766D
+P 18450 8300
+F 0 "U1" H 18500 8400 30  0000 C CNN
+F 1 "PORT" H 18450 8300 30  0000 C CNN
+F 2 "" H 18450 8300 60  0000 C CNN
+F 3 "" H 18450 8300 60  0000 C CNN
+	10   18450 8300
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	18200 8300 17900 8300
+Wire Wire Line
+	18200 8450 17900 8450
+Wire Wire Line
+	17900 8450 17900 8400
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.sub b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.sub
new file mode 100644
index 00000000..7800040c
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.sub
@@ -0,0 +1,102 @@
+* Subcircuit CD4078B_IC
+.subckt CD4078B_IC net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ 
+* d:\fossee\esim\library\subcircuitlibrary\cd4078b_ic\cd4078b_ic.cir
+* u3  net-_u2-pad9_ net-_u11-pad1_ d_inverter
+* u4  net-_u2-pad10_ net-_u11-pad2_ d_inverter
+* u5  net-_u2-pad11_ net-_u12-pad1_ d_inverter
+* u6  net-_u2-pad12_ net-_u12-pad2_ d_inverter
+* u7  net-_u2-pad13_ net-_u13-pad1_ d_inverter
+* u8  net-_u2-pad14_ net-_u13-pad2_ d_inverter
+* u9  net-_u2-pad15_ net-_u14-pad1_ d_inverter
+* u10  net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u21  net-_u19-pad3_ net-_u20-pad3_ net-_u21-pad3_ d_nor
+* u22  net-_u21-pad3_ net-_u22-pad2_ d_inverter
+* u24  net-_u22-pad2_ net-_u24-pad2_ d_inverter
+* u23  net-_u21-pad3_ net-_u23-pad2_ d_inverter
+* u25  net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad10_ net-_u1-pad9_ dac_bridge_2
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ adc_bridge_8
+* u11  net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand
+* u12  net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nand
+* u15  net-_u11-pad3_ net-_u11-pad3_ net-_u15-pad3_ d_nand
+* u16  net-_u12-pad3_ net-_u12-pad3_ net-_u16-pad3_ d_nand
+* u19  net-_u15-pad3_ net-_u16-pad3_ net-_u19-pad3_ d_nand
+* u13  net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nand
+* u14  net-_u14-pad1_ net-_u10-pad2_ net-_u14-pad3_ d_nand
+* u17  net-_u13-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nand
+* u18  net-_u14-pad3_ net-_u14-pad3_ net-_u18-pad3_ d_nand
+* u20  net-_u17-pad3_ net-_u18-pad3_ net-_u20-pad3_ d_nand
+a1 net-_u2-pad9_ net-_u11-pad1_ u3
+a2 net-_u2-pad10_ net-_u11-pad2_ u4
+a3 net-_u2-pad11_ net-_u12-pad1_ u5
+a4 net-_u2-pad12_ net-_u12-pad2_ u6
+a5 net-_u2-pad13_ net-_u13-pad1_ u7
+a6 net-_u2-pad14_ net-_u13-pad2_ u8
+a7 net-_u2-pad15_ net-_u14-pad1_ u9
+a8 net-_u10-pad1_ net-_u10-pad2_ u10
+a9 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u21-pad3_ u21
+a10 net-_u21-pad3_ net-_u22-pad2_ u22
+a11 net-_u22-pad2_ net-_u24-pad2_ u24
+a12 net-_u21-pad3_ net-_u23-pad2_ u23
+a13 [net-_u24-pad2_ net-_u23-pad2_ ] [net-_u1-pad10_ net-_u1-pad9_ ] u25
+a14 [net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] [net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ ] u2
+a15 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a16 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a17 [net-_u11-pad3_ net-_u11-pad3_ ] net-_u15-pad3_ u15
+a18 [net-_u12-pad3_ net-_u12-pad3_ ] net-_u16-pad3_ u16
+a19 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u19-pad3_ u19
+a20 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a21 [net-_u14-pad1_ net-_u10-pad2_ ] net-_u14-pad3_ u14
+a22 [net-_u13-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17
+a23 [net-_u14-pad3_ net-_u14-pad3_ ] net-_u18-pad3_ u18
+a24 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u20-pad3_ u20
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u21 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_2, NgSpice Name: dac_bridge
+.model u25 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_8, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u20 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends CD4078B_IC
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC_Previous_Values.xml b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC_Previous_Values.xml
new file mode 100644
index 00000000..821bf547
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u3 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u10><u21 name="type">d_nor<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u21><u22 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u22><u24 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u24><u23 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u23><u25 name="type">dac_bridge<field37 name="Enter value for out_low (default=0.0)" /><field38 name="Enter value for out_high (default=5.0)" /><field39 name="Enter value for out_undef (default=0.5)" /><field40 name="Enter value for input load (default=1.0e-12)" /><field41 name="Enter the Rise Time (default=1.0e-9)" /><field42 name="Enter the Fall Time (default=1.0e-9)" /></u25><u2 name="type">adc_bridge<field43 name="Enter value for in_low (default=1.0)" /><field44 name="Enter value for in_high (default=2.0)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /><field46 name="Enter Fall Delay (default=1.0e-9)" /></u2><u11 name="type">d_nand<field47 name="Enter Rise Delay (default=1.0e-9)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_nand<field50 name="Enter Rise Delay (default=1.0e-9)" /><field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /></u12><u15 name="type">d_nand<field53 name="Enter Rise Delay (default=1.0e-9)" /><field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">d_nand<field56 name="Enter Rise Delay (default=1.0e-9)" /><field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /></u16><u19 name="type">d_nand<field59 name="Enter Rise Delay (default=1.0e-9)" /><field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /></u19><u13 name="type">d_nand<field62 name="Enter Rise Delay (default=1.0e-9)" /><field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_nand<field65 name="Enter Rise Delay (default=1.0e-9)" /><field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /></u14><u17 name="type">d_nand<field68 name="Enter Rise Delay (default=1.0e-9)" /><field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_nand<field71 name="Enter Rise Delay (default=1.0e-9)" /><field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /></u18><u20 name="type">d_nand<field74 name="Enter Rise Delay (default=1.0e-9)" /><field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /></u20></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0.01</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4078B_sub/analysis b/library/SubcircuitLibrary/CD4078B_sub/analysis
new file mode 100644
index 00000000..db9906e6
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4078B_sub/analysis
@@ -0,0 +1 @@
+.tran 0.01e-03 100e-03 0e-00
\ No newline at end of file