HD74LS139 as a dual 2:4 decoder/ demultiplexer IC

8 files changed, 1053 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/HD74LS139/74139-cache.lib b/library/SubcircuitLibrary/HD74LS139/74139-cache.lib
new file mode 100644
index 00000000..ca3dbb87
--- /dev/null
+++ b/library/SubcircuitLibrary/HD74LS139/74139-cache.lib
@@ -0,0 +1,76 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/HD74LS139/74139.cir b/library/SubcircuitLibrary/HD74LS139/74139.cir
new file mode 100644
index 00000000..4df10d23
--- /dev/null
+++ b/library/SubcircuitLibrary/HD74LS139/74139.cir
@@ -0,0 +1,37 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74139\74139.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 04/21/25 11:14:27
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X5  Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U2-Pad2_ Net-_U13-Pad1_ 3_and		
+U13  Net-_U13-Pad1_ Net-_U1-Pad7_ d_inverter		
+X6  Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U14-Pad1_ 3_and		
+U14  Net-_U14-Pad1_ Net-_U1-Pad8_ d_inverter		
+X7  Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U6-Pad2_ Net-_U18-Pad1_ 3_and		
+U18  Net-_U18-Pad1_ Net-_U1-Pad9_ d_inverter		
+X8  Net-_U2-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U15-Pad1_ 3_and		
+U15  Net-_U15-Pad1_ Net-_U1-Pad10_ d_inverter		
+X1  Net-_U11-Pad1_ Net-_U10-Pad1_ Net-_U7-Pad2_ Net-_U19-Pad1_ 3_and		
+U19  Net-_U19-Pad1_ Net-_U1-Pad11_ d_inverter		
+X2  Net-_U7-Pad2_ Net-_U10-Pad1_ Net-_U11-Pad2_ Net-_U16-Pad1_ 3_and		
+U16  Net-_U16-Pad1_ Net-_U1-Pad12_ d_inverter		
+X3  Net-_U7-Pad2_ Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U17-Pad1_ 3_and		
+U17  Net-_U17-Pad1_ Net-_U1-Pad13_ d_inverter		
+X4  Net-_U7-Pad2_ Net-_U11-Pad2_ Net-_U10-Pad2_ Net-_U12-Pad1_ 3_and		
+U12  Net-_U12-Pad1_ Net-_U1-Pad14_ d_inverter		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT		
+U2  Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter		
+U3  Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter		
+U5  Net-_U3-Pad2_ Net-_U5-Pad2_ d_inverter		
+U4  Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter		
+U6  Net-_U4-Pad2_ Net-_U6-Pad2_ d_inverter		
+U7  Net-_U1-Pad4_ Net-_U7-Pad2_ d_inverter		
+U9  Net-_U1-Pad5_ Net-_U11-Pad1_ d_inverter		
+U11  Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter		
+U8  Net-_U1-Pad6_ Net-_U10-Pad1_ d_inverter		
+U10  Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter		
+
+.end
diff --git a/library/SubcircuitLibrary/HD74LS139/74139.cir.out b/library/SubcircuitLibrary/HD74LS139/74139.cir.out
new file mode 100644
index 00000000..21304303
--- /dev/null
+++ b/library/SubcircuitLibrary/HD74LS139/74139.cir.out
@@ -0,0 +1,93 @@
+* c:\fossee\esim\library\subcircuitlibrary\74139\74139.cir
+
+.include 3_and.sub
+x5 net-_u3-pad2_ net-_u4-pad2_ net-_u2-pad2_ net-_u13-pad1_ 3_and
+* u13  net-_u13-pad1_ net-_u1-pad7_ d_inverter
+x6 net-_u2-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u14-pad1_ 3_and
+* u14  net-_u14-pad1_ net-_u1-pad8_ d_inverter
+x7 net-_u2-pad2_ net-_u3-pad2_ net-_u6-pad2_ net-_u18-pad1_ 3_and
+* u18  net-_u18-pad1_ net-_u1-pad9_ d_inverter
+x8 net-_u2-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u15-pad1_ 3_and
+* u15  net-_u15-pad1_ net-_u1-pad10_ d_inverter
+x1 net-_u11-pad1_ net-_u10-pad1_ net-_u7-pad2_ net-_u19-pad1_ 3_and
+* u19  net-_u19-pad1_ net-_u1-pad11_ d_inverter
+x2 net-_u7-pad2_ net-_u10-pad1_ net-_u11-pad2_ net-_u16-pad1_ 3_and
+* u16  net-_u16-pad1_ net-_u1-pad12_ d_inverter
+x3 net-_u7-pad2_ net-_u11-pad1_ net-_u10-pad2_ net-_u17-pad1_ 3_and
+* u17  net-_u17-pad1_ net-_u1-pad13_ d_inverter
+x4 net-_u7-pad2_ net-_u11-pad2_ net-_u10-pad2_ net-_u12-pad1_ 3_and
+* u12  net-_u12-pad1_ net-_u1-pad14_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
+* u5  net-_u3-pad2_ net-_u5-pad2_ d_inverter
+* u4  net-_u1-pad3_ net-_u4-pad2_ d_inverter
+* u6  net-_u4-pad2_ net-_u6-pad2_ d_inverter
+* u7  net-_u1-pad4_ net-_u7-pad2_ d_inverter
+* u9  net-_u1-pad5_ net-_u11-pad1_ d_inverter
+* u11  net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u8  net-_u1-pad6_ net-_u10-pad1_ d_inverter
+* u10  net-_u10-pad1_ net-_u10-pad2_ d_inverter
+a1 net-_u13-pad1_ net-_u1-pad7_ u13
+a2 net-_u14-pad1_ net-_u1-pad8_ u14
+a3 net-_u18-pad1_ net-_u1-pad9_ u18
+a4 net-_u15-pad1_ net-_u1-pad10_ u15
+a5 net-_u19-pad1_ net-_u1-pad11_ u19
+a6 net-_u16-pad1_ net-_u1-pad12_ u16
+a7 net-_u17-pad1_ net-_u1-pad13_ u17
+a8 net-_u12-pad1_ net-_u1-pad14_ u12
+a9 net-_u1-pad1_ net-_u2-pad2_ u2
+a10 net-_u1-pad2_ net-_u3-pad2_ u3
+a11 net-_u3-pad2_ net-_u5-pad2_ u5
+a12 net-_u1-pad3_ net-_u4-pad2_ u4
+a13 net-_u4-pad2_ net-_u6-pad2_ u6
+a14 net-_u1-pad4_ net-_u7-pad2_ u7
+a15 net-_u1-pad5_ net-_u11-pad1_ u9
+a16 net-_u11-pad1_ net-_u11-pad2_ u11
+a17 net-_u1-pad6_ net-_u10-pad1_ u8
+a18 net-_u10-pad1_ net-_u10-pad2_ u10
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/HD74LS139/74139.pro b/library/SubcircuitLibrary/HD74LS139/74139.pro
new file mode 100644
index 00000000..82579415
--- /dev/null
+++ b/library/SubcircuitLibrary/HD74LS139/74139.pro
@@ -0,0 +1,83 @@
+update=05/06/25 21:01:46
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceForceRefPrefix=0
+SpiceUseNetNumbers=0
+LabSize=60
diff --git a/library/SubcircuitLibrary/HD74LS139/74139.sch b/library/SubcircuitLibrary/HD74LS139/74139.sch
new file mode 100644
index 00000000..ac975979
--- /dev/null
+++ b/library/SubcircuitLibrary/HD74LS139/74139.sch
@@ -0,0 +1,675 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:74139-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and X5
+U 1 1 6805C3A6
+P 8650 1300
+F 0 "X5" H 8750 1250 60  0000 C CNN
+F 1 "3_and" H 8800 1450 60  0000 C CNN
+F 2 "" H 8650 1300 60  0000 C CNN
+F 3 "" H 8650 1300 60  0000 C CNN
+	1    8650 1300
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U13
+U 1 1 6805C41F
+P 9600 1250
+F 0 "U13" H 9600 1150 60  0000 C CNN
+F 1 "d_inverter" H 9600 1400 60  0000 C CNN
+F 2 "" H 9650 1200 60  0000 C CNN
+F 3 "" H 9650 1200 60  0000 C CNN
+	1    9600 1250
+	1    0    0    -1  
+$EndComp
+$Comp
+L 3_and X6
+U 1 1 6805C440
+P 8650 1900
+F 0 "X6" H 8750 1850 60  0000 C CNN
+F 1 "3_and" H 8800 2050 60  0000 C CNN
+F 2 "" H 8650 1900 60  0000 C CNN
+F 3 "" H 8650 1900 60  0000 C CNN
+	1    8650 1900
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U14
+U 1 1 6805C46B
+P 9600 1850
+F 0 "U14" H 9600 1750 60  0000 C CNN
+F 1 "d_inverter" H 9600 2000 60  0000 C CNN
+F 2 "" H 9650 1800 60  0000 C CNN
+F 3 "" H 9650 1800 60  0000 C CNN
+	1    9600 1850
+	1    0    0    -1  
+$EndComp
+$Comp
+L 3_and X7
+U 1 1 6805C48A
+P 8650 2500
+F 0 "X7" H 8750 2450 60  0000 C CNN
+F 1 "3_and" H 8800 2650 60  0000 C CNN
+F 2 "" H 8650 2500 60  0000 C CNN
+F 3 "" H 8650 2500 60  0000 C CNN
+	1    8650 2500
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U18
+U 1 1 6805C4B7
+P 9650 2450
+F 0 "U18" H 9650 2350 60  0000 C CNN
+F 1 "d_inverter" H 9650 2600 60  0000 C CNN
+F 2 "" H 9700 2400 60  0000 C CNN
+F 3 "" H 9700 2400 60  0000 C CNN
+	1    9650 2450
+	1    0    0    -1  
+$EndComp
+$Comp
+L 3_and X8
+U 1 1 6805C4DC
+P 8650 3050
+F 0 "X8" H 8750 3000 60  0000 C CNN
+F 1 "3_and" H 8800 3200 60  0000 C CNN
+F 2 "" H 8650 3050 60  0000 C CNN
+F 3 "" H 8650 3050 60  0000 C CNN
+	1    8650 3050
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U15
+U 1 1 6805C513
+P 9600 3000
+F 0 "U15" H 9600 2900 60  0000 C CNN
+F 1 "d_inverter" H 9600 3150 60  0000 C CNN
+F 2 "" H 9650 2950 60  0000 C CNN
+F 3 "" H 9650 2950 60  0000 C CNN
+	1    9600 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L 3_and X1
+U 1 1 6805C538
+P 8600 3950
+F 0 "X1" H 8700 3900 60  0000 C CNN
+F 1 "3_and" H 8750 4100 60  0000 C CNN
+F 2 "" H 8600 3950 60  0000 C CNN
+F 3 "" H 8600 3950 60  0000 C CNN
+	1    8600 3950
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U19
+U 1 1 6805C573
+P 9650 3900
+F 0 "U19" H 9650 3800 60  0000 C CNN
+F 1 "d_inverter" H 9650 4050 60  0000 C CNN
+F 2 "" H 9700 3850 60  0000 C CNN
+F 3 "" H 9700 3850 60  0000 C CNN
+	1    9650 3900
+	1    0    0    -1  
+$EndComp
+$Comp
+L 3_and X2
+U 1 1 6805C5A4
+P 8600 4450
+F 0 "X2" H 8700 4400 60  0000 C CNN
+F 1 "3_and" H 8750 4600 60  0000 C CNN
+F 2 "" H 8600 4450 60  0000 C CNN
+F 3 "" H 8600 4450 60  0000 C CNN
+	1    8600 4450
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U16
+U 1 1 6805C5D3
+P 9600 4400
+F 0 "U16" H 9600 4300 60  0000 C CNN
+F 1 "d_inverter" H 9600 4550 60  0000 C CNN
+F 2 "" H 9650 4350 60  0000 C CNN
+F 3 "" H 9650 4350 60  0000 C CNN
+	1    9600 4400
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+$EndComp
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+F 0 "X3" H 8700 4950 60  0000 C CNN
+F 1 "3_and" H 8750 5150 60  0000 C CNN
+F 2 "" H 8600 5000 60  0000 C CNN
+F 3 "" H 8600 5000 60  0000 C CNN
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+	1    0    0    -1  
+$EndComp
+$Comp
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+F 0 "U17" H 9600 4850 60  0000 C CNN
+F 1 "d_inverter" H 9600 5100 60  0000 C CNN
+F 2 "" H 9650 4900 60  0000 C CNN
+F 3 "" H 9650 4900 60  0000 C CNN
+	1    9600 4950
+	1    0    0    -1  
+$EndComp
+$Comp
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+F 2 "" H 8600 5450 60  0000 C CNN
+F 3 "" H 8600 5450 60  0000 C CNN
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+$Comp
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+F 0 "U12" H 9550 5300 60  0000 C CNN
+F 1 "d_inverter" H 9550 5550 60  0000 C CNN
+F 2 "" H 9600 5350 60  0000 C CNN
+F 3 "" H 9600 5350 60  0000 C CNN
+	1    9550 5400
+	1    0    0    -1  
+$EndComp
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+	9900 4950 10300 4950
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	4300 3900 8250 3900
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	7550 5300 8250 5300
+Wire Wire Line
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+Wire Wire Line
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+U 1 1 6805D472
+P 1350 1150
+F 0 "U1" H 1400 1250 30  0000 C CNN
+F 1 "PORT" H 1350 1150 30  0000 C CNN
+F 2 "" H 1350 1150 60  0000 C CNN
+F 3 "" H 1350 1150 60  0000 C CNN
+	1    1350 1150
+	1    0    0    -1  
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+$Comp
+L PORT U1
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+F 0 "U1" H 2300 2150 30  0000 C CNN
+F 1 "PORT" H 2250 2050 30  0000 C CNN
+F 2 "" H 2250 2050 60  0000 C CNN
+F 3 "" H 2250 2050 60  0000 C CNN
+	2    2250 2050
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6805D51C
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+F 0 "U1" H 2300 2650 30  0000 C CNN
+F 1 "PORT" H 2250 2550 30  0000 C CNN
+F 2 "" H 2250 2550 60  0000 C CNN
+F 3 "" H 2250 2550 60  0000 C CNN
+	3    2250 2550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6805D640
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+F 0 "U1" H 1500 4300 30  0000 C CNN
+F 1 "PORT" H 1450 4200 30  0000 C CNN
+F 2 "" H 1450 4200 60  0000 C CNN
+F 3 "" H 1450 4200 60  0000 C CNN
+	4    1450 4200
+	1    0    0    -1  
+$EndComp
+$Comp
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+U 5 1 6805D69B
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+F 0 "U1" H 2400 5100 30  0000 C CNN
+F 1 "PORT" H 2350 5000 30  0000 C CNN
+F 2 "" H 2350 5000 60  0000 C CNN
+F 3 "" H 2350 5000 60  0000 C CNN
+	5    2350 5000
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6805D7CD
+P 2350 5450
+F 0 "U1" H 2400 5550 30  0000 C CNN
+F 1 "PORT" H 2350 5450 30  0000 C CNN
+F 2 "" H 2350 5450 60  0000 C CNN
+F 3 "" H 2350 5450 60  0000 C CNN
+	6    2350 5450
+	1    0    0    -1  
+$EndComp
+$Comp
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+F 0 "U1" H 10600 1350 30  0000 C CNN
+F 1 "PORT" H 10550 1250 30  0000 C CNN
+F 2 "" H 10550 1250 60  0000 C CNN
+F 3 "" H 10550 1250 60  0000 C CNN
+	7    10550 1250
+	-1   0    0    1   
+$EndComp
+$Comp
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+U 8 1 6805DA57
+P 10550 1850
+F 0 "U1" H 10600 1950 30  0000 C CNN
+F 1 "PORT" H 10550 1850 30  0000 C CNN
+F 2 "" H 10550 1850 60  0000 C CNN
+F 3 "" H 10550 1850 60  0000 C CNN
+	8    10550 1850
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6805DABE
+P 10550 2450
+F 0 "U1" H 10600 2550 30  0000 C CNN
+F 1 "PORT" H 10550 2450 30  0000 C CNN
+F 2 "" H 10550 2450 60  0000 C CNN
+F 3 "" H 10550 2450 60  0000 C CNN
+	9    10550 2450
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6805DC41
+P 10550 3000
+F 0 "U1" H 10600 3100 30  0000 C CNN
+F 1 "PORT" H 10550 3000 30  0000 C CNN
+F 2 "" H 10550 3000 60  0000 C CNN
+F 3 "" H 10550 3000 60  0000 C CNN
+	10   10550 3000
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6805DCB2
+P 10550 3900
+F 0 "U1" H 10600 4000 30  0000 C CNN
+F 1 "PORT" H 10550 3900 30  0000 C CNN
+F 2 "" H 10550 3900 60  0000 C CNN
+F 3 "" H 10550 3900 60  0000 C CNN
+	11   10550 3900
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 12 1 6805DD1D
+P 10550 4350
+F 0 "U1" H 10600 4450 30  0000 C CNN
+F 1 "PORT" H 10550 4350 30  0000 C CNN
+F 2 "" H 10550 4350 60  0000 C CNN
+F 3 "" H 10550 4350 60  0000 C CNN
+	12   10550 4350
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 13 1 6805DD94
+P 10550 4950
+F 0 "U1" H 10600 5050 30  0000 C CNN
+F 1 "PORT" H 10550 4950 30  0000 C CNN
+F 2 "" H 10550 4950 60  0000 C CNN
+F 3 "" H 10550 4950 60  0000 C CNN
+	13   10550 4950
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 14 1 6805DF1C
+P 10550 5400
+F 0 "U1" H 10600 5500 30  0000 C CNN
+F 1 "PORT" H 10550 5400 30  0000 C CNN
+F 2 "" H 10550 5400 60  0000 C CNN
+F 3 "" H 10550 5400 60  0000 C CNN
+	14   10550 5400
+	-1   0    0    1   
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 6805F0D7
+P 2600 1150
+F 0 "U2" H 2600 1050 60  0000 C CNN
+F 1 "d_inverter" H 2600 1300 60  0000 C CNN
+F 2 "" H 2650 1100 60  0000 C CNN
+F 3 "" H 2650 1100 60  0000 C CNN
+	1    2600 1150
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	1600 1150 2300 1150
+Wire Wire Line
+	2900 1150 7000 1150
+$Comp
+L d_inverter U3
+U 1 1 6805F313
+P 3300 2100
+F 0 "U3" H 3300 2000 60  0000 C CNN
+F 1 "d_inverter" H 3300 2250 60  0000 C CNN
+F 2 "" H 3350 2050 60  0000 C CNN
+F 3 "" H 3350 2050 60  0000 C CNN
+	1    3300 2100
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U5
+U 1 1 6805F378
+P 4750 2100
+F 0 "U5" H 4750 2000 60  0000 C CNN
+F 1 "d_inverter" H 4750 2250 60  0000 C CNN
+F 2 "" H 4800 2050 60  0000 C CNN
+F 3 "" H 4800 2050 60  0000 C CNN
+	1    4750 2100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3600 2100 4450 2100
+Wire Wire Line
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+$Comp
+L d_inverter U4
+U 1 1 6805F4EB
+P 3350 2550
+F 0 "U4" H 3350 2450 60  0000 C CNN
+F 1 "d_inverter" H 3350 2700 60  0000 C CNN
+F 2 "" H 3400 2500 60  0000 C CNN
+F 3 "" H 3400 2500 60  0000 C CNN
+	1    3350 2550
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 6805F546
+P 4750 2550
+F 0 "U6" H 4750 2450 60  0000 C CNN
+F 1 "d_inverter" H 4750 2700 60  0000 C CNN
+F 2 "" H 4800 2500 60  0000 C CNN
+F 3 "" H 4800 2500 60  0000 C CNN
+	1    4750 2550
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2500 2550 3050 2550
+Wire Wire Line
+	3650 2550 4450 2550
+Wire Wire Line
+	5050 2550 6400 2550
+$Comp
+L d_inverter U7
+U 1 1 6805F904
+P 2450 4200
+F 0 "U7" H 2450 4100 60  0000 C CNN
+F 1 "d_inverter" H 2450 4350 60  0000 C CNN
+F 2 "" H 2500 4150 60  0000 C CNN
+F 3 "" H 2500 4150 60  0000 C CNN
+	1    2450 4200
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	1700 4200 2150 4200
+Wire Wire Line
+	2750 4200 8250 4200
+$Comp
+L d_inverter U9
+U 1 1 6805FB1C
+P 3250 5000
+F 0 "U9" H 3250 4900 60  0000 C CNN
+F 1 "d_inverter" H 3250 5150 60  0000 C CNN
+F 2 "" H 3300 4950 60  0000 C CNN
+F 3 "" H 3300 4950 60  0000 C CNN
+	1    3250 5000
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U11
+U 1 1 6805FB7B
+P 4900 5000
+F 0 "U11" H 4900 4900 60  0000 C CNN
+F 1 "d_inverter" H 4900 5150 60  0000 C CNN
+F 2 "" H 4950 4950 60  0000 C CNN
+F 3 "" H 4950 4950 60  0000 C CNN
+	1    4900 5000
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U8
+U 1 1 6805FC04
+P 3200 5450
+F 0 "U8" H 3200 5350 60  0000 C CNN
+F 1 "d_inverter" H 3200 5600 60  0000 C CNN
+F 2 "" H 3250 5400 60  0000 C CNN
+F 3 "" H 3250 5400 60  0000 C CNN
+	1    3200 5450
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U10
+U 1 1 6805FC67
+P 4850 5450
+F 0 "U10" H 4850 5350 60  0000 C CNN
+F 1 "d_inverter" H 4850 5600 60  0000 C CNN
+F 2 "" H 4900 5400 60  0000 C CNN
+F 3 "" H 4900 5400 60  0000 C CNN
+	1    4850 5450
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2600 5000 2950 5000
+Wire Wire Line
+	2600 5450 2900 5450
+Wire Wire Line
+	3550 5000 4600 5000
+Wire Wire Line
+	3500 5450 4550 5450
+Wire Wire Line
+	7050 5000 5200 5000
+Wire Wire Line
+	7050 4500 7050 5400
+Wire Wire Line
+	5150 5450 7800 5450
+Connection ~ 7550 4200
+Connection ~ 7650 1750
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/HD74LS139/74139.sub b/library/SubcircuitLibrary/HD74LS139/74139.sub
new file mode 100644
index 00000000..f044a755
--- /dev/null
+++ b/library/SubcircuitLibrary/HD74LS139/74139.sub
@@ -0,0 +1,87 @@
+* Subcircuit 74139
+.subckt 74139 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ 
+* c:\fossee\esim\library\subcircuitlibrary\74139\74139.cir
+.include 3_and.sub
+x5 net-_u3-pad2_ net-_u4-pad2_ net-_u2-pad2_ net-_u13-pad1_ 3_and
+* u13  net-_u13-pad1_ net-_u1-pad7_ d_inverter
+x6 net-_u2-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u14-pad1_ 3_and
+* u14  net-_u14-pad1_ net-_u1-pad8_ d_inverter
+x7 net-_u2-pad2_ net-_u3-pad2_ net-_u6-pad2_ net-_u18-pad1_ 3_and
+* u18  net-_u18-pad1_ net-_u1-pad9_ d_inverter
+x8 net-_u2-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u15-pad1_ 3_and
+* u15  net-_u15-pad1_ net-_u1-pad10_ d_inverter
+x1 net-_u11-pad1_ net-_u10-pad1_ net-_u7-pad2_ net-_u19-pad1_ 3_and
+* u19  net-_u19-pad1_ net-_u1-pad11_ d_inverter
+x2 net-_u7-pad2_ net-_u10-pad1_ net-_u11-pad2_ net-_u16-pad1_ 3_and
+* u16  net-_u16-pad1_ net-_u1-pad12_ d_inverter
+x3 net-_u7-pad2_ net-_u11-pad1_ net-_u10-pad2_ net-_u17-pad1_ 3_and
+* u17  net-_u17-pad1_ net-_u1-pad13_ d_inverter
+x4 net-_u7-pad2_ net-_u11-pad2_ net-_u10-pad2_ net-_u12-pad1_ 3_and
+* u12  net-_u12-pad1_ net-_u1-pad14_ d_inverter
+* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
+* u5  net-_u3-pad2_ net-_u5-pad2_ d_inverter
+* u4  net-_u1-pad3_ net-_u4-pad2_ d_inverter
+* u6  net-_u4-pad2_ net-_u6-pad2_ d_inverter
+* u7  net-_u1-pad4_ net-_u7-pad2_ d_inverter
+* u9  net-_u1-pad5_ net-_u11-pad1_ d_inverter
+* u11  net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u8  net-_u1-pad6_ net-_u10-pad1_ d_inverter
+* u10  net-_u10-pad1_ net-_u10-pad2_ d_inverter
+a1 net-_u13-pad1_ net-_u1-pad7_ u13
+a2 net-_u14-pad1_ net-_u1-pad8_ u14
+a3 net-_u18-pad1_ net-_u1-pad9_ u18
+a4 net-_u15-pad1_ net-_u1-pad10_ u15
+a5 net-_u19-pad1_ net-_u1-pad11_ u19
+a6 net-_u16-pad1_ net-_u1-pad12_ u16
+a7 net-_u17-pad1_ net-_u1-pad13_ u17
+a8 net-_u12-pad1_ net-_u1-pad14_ u12
+a9 net-_u1-pad1_ net-_u2-pad2_ u2
+a10 net-_u1-pad2_ net-_u3-pad2_ u3
+a11 net-_u3-pad2_ net-_u5-pad2_ u5
+a12 net-_u1-pad3_ net-_u4-pad2_ u4
+a13 net-_u4-pad2_ net-_u6-pad2_ u6
+a14 net-_u1-pad4_ net-_u7-pad2_ u7
+a15 net-_u1-pad5_ net-_u11-pad1_ u9
+a16 net-_u11-pad1_ net-_u11-pad2_ u11
+a17 net-_u1-pad6_ net-_u10-pad1_ u8
+a18 net-_u10-pad1_ net-_u10-pad2_ u10
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74139
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/HD74LS139/74139_Previous_Values.xml b/library/SubcircuitLibrary/HD74LS139/74139_Previous_Values.xml
new file mode 100644
index 00000000..7328b6f2
--- /dev/null
+++ b/library/SubcircuitLibrary/HD74LS139/74139_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u13 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u14><u18 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u18><u15 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u15><u19 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u19><u16 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u16><u17 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u17><u12 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u12><u2 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u4><u8 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u9><u5 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u7><u10 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u11><u2 name="type">d_buffer<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u2><u5 name="type">d_buffer<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u5></model><devicemodel /><subcircuit><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x5><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x6><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x7><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x8><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x3><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/HD74LS139/analysis b/library/SubcircuitLibrary/HD74LS139/analysis
new file mode 100644
index 00000000..2e3711be
--- /dev/null
+++ b/library/SubcircuitLibrary/HD74LS139/analysis
@@ -0,0 +1 @@
+.tran 10e-03 13e-00 0e-03
\ No newline at end of file