diff options
Diffstat (limited to 'RLC')
| -rw-r--r-- | RLC/RLC-cache.lib | 109 | ||||
| -rw-r--r-- | RLC/RLC.bak | 141 | ||||
| -rw-r--r-- | RLC/RLC.cir | 16 | ||||
| -rw-r--r-- | RLC/RLC.cir.out | 19 | ||||
| -rw-r--r-- | RLC/RLC.pro | 71 | ||||
| -rw-r--r-- | RLC/RLC.proj | 1 | ||||
| -rw-r--r-- | RLC/RLC.sch | 167 | ||||
| -rw-r--r-- | RLC/RLC_Previous_Values.xml | 1 | ||||
| -rw-r--r-- | RLC/analysis | 1 | ||||
| -rw-r--r-- | RLC/plot_data_i.txt | 149 | ||||
| -rw-r--r-- | RLC/plot_data_v.txt | 149 |
11 files changed, 824 insertions, 0 deletions
diff --git a/RLC/RLC-cache.lib b/RLC/RLC-cache.lib new file mode 100644 index 0000000..14bc7de --- /dev/null +++ b/RLC/RLC-cache.lib @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C? + C_????_* + C_???? + SMD*_c + Capacitor* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# L +# +DEF L L 0 40 N N 1 F N +F0 "L" 1950 500 50 H V C CNN +F1 "L" 1950 650 50 H V C CNN +F2 "" 1950 550 60 V V C CNN +F3 "" 1950 550 60 V V C CNN +DRAW +A 1802 550 48 11 1789 0 1 0 N 1849 551 1754 551 +A 1899 550 51 11 1789 0 1 0 N 1949 551 1848 551 +A 1999 550 51 11 1789 0 1 0 N 2049 551 1948 551 +A 2100 550 50 11 1789 0 1 0 N 2149 551 2050 551 +X 1 1 1650 550 100 R 70 70 1 1 P +X 2 2 2250 550 100 L 70 70 1 1 P +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pwl +# +DEF pwl v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pwl" -250 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -1144 -561 1253 291 240 0 1 0 N -50 50 0 -50 +A -765 421 941 -300 -232 0 1 0 N 50 -50 100 50 +A -75 -700 750 919 880 0 1 0 N -100 50 -50 50 +A 25 450 501 -928 -871 0 1 0 N 0 -50 50 -50 +A 1096 -609 1366 1511 1558 0 1 0 N -100 50 -150 -50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/RLC/RLC.bak b/RLC/RLC.bak new file mode 100644 index 0000000..0c17307 --- /dev/null +++ b/RLC/RLC.bak @@ -0,0 +1,141 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L R R1 +U 1 1 56C172A1 +P 4850 2700 +F 0 "R1" H 4900 2830 50 0000 C CNN +F 1 "1k" H 4900 2750 50 0000 C CNN +F 2 "" H 4900 2680 30 0000 C CNN +F 3 "" V 4900 2750 30 0000 C CNN + 1 4850 2700 + 1 0 0 -1 +$EndComp +$Comp +L L L1 +U 1 1 56C172D6 +P 3800 3200 +F 0 "L1" H 5750 3700 50 0000 C CNN +F 1 "2" H 5750 3850 50 0000 C CNN +F 2 "" V 5750 3750 60 0000 C CNN +F 3 "" V 5750 3750 60 0000 C CNN + 1 3800 3200 + 1 0 0 -1 +$EndComp +$Comp +L C C1 +U 1 1 56C17369 +P 6400 3350 +F 0 "C1" H 6425 3450 50 0000 L CNN +F 1 "0.5u" H 6425 3250 50 0000 L CNN +F 2 "" H 6438 3200 30 0000 C CNN +F 3 "" H 6400 3350 60 0000 C CNN + 1 6400 3350 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 56C173A6 +P 5400 3900 +F 0 "#PWR01" H 5400 3650 50 0001 C CNN +F 1 "GND" H 5400 3750 50 0000 C CNN +F 2 "" H 5400 3900 50 0000 C CNN +F 3 "" H 5400 3900 50 0000 C CNN + 1 5400 3900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4200 2850 4200 2650 +Wire Wire Line + 4200 2650 4750 2650 +Wire Wire Line + 5050 2650 5450 2650 +Wire Wire Line + 6050 2650 6400 2650 +Wire Wire Line + 6400 2650 6400 3200 +Wire Wire Line + 4200 3750 4200 3850 +Wire Wire Line + 4200 3850 6400 3850 +Wire Wire Line + 6400 3850 6400 3500 +Wire Wire Line + 5400 3900 5400 3850 +Connection ~ 5400 3850 +Text GLabel 4200 2500 0 60 Input ~ 0 +in +Text GLabel 6400 2500 2 60 Input ~ 0 +out +Wire Wire Line + 4200 2500 4250 2500 +Wire Wire Line + 4250 2500 4250 2650 +Connection ~ 4250 2650 +Wire Wire Line + 6400 2500 6350 2500 +Wire Wire Line + 6350 2500 6350 2650 +Connection ~ 6350 2650 +$Comp +L pwl v1 +U 1 1 56C17805 +P 4200 3300 +F 0 "v1" H 4000 3400 60 0000 C CNN +F 1 "pwl" H 3950 3250 60 0000 C CNN +F 2 "R1" H 3900 3300 60 0000 C CNN +F 3 "" H 4200 3300 60 0000 C CNN + 1 4200 3300 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/RLC/RLC.cir b/RLC/RLC.cir new file mode 100644 index 0000000..249b055 --- /dev/null +++ b/RLC/RLC.cir @@ -0,0 +1,16 @@ +* /home/fossee/eSim-Workspace/RLC/RLC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Feb 29 21:39:24 2016 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 in Net-_L1-Pad1_ 1k +L1 Net-_L1-Pad1_ out 2 +C1 out GND 0.5u +v1 in GND pwl +U1 in plot_v1 +U2 out plot_v1 + +.end diff --git a/RLC/RLC.cir.out b/RLC/RLC.cir.out new file mode 100644 index 0000000..6498043 --- /dev/null +++ b/RLC/RLC.cir.out @@ -0,0 +1,19 @@ +* /home/fossee/esim-workspace/rlc/rlc.cir + +r1 in net-_l1-pad1_ 1k +l1 net-_l1-pad1_ out 2 +c1 out gnd 0.5u +v1 in gnd pwl(0m 0 0.5m 5) +* u1 in plot_v1 +* u2 out plot_v1 +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in) +plot v(out) +.endc +.end diff --git a/RLC/RLC.pro b/RLC/RLC.pro new file mode 100644 index 0000000..3f26d6b --- /dev/null +++ b/RLC/RLC.pro @@ -0,0 +1,71 @@ +update=Mon Feb 29 21:38:45 2016 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User +LibName11=adc-dac +LibName12=memory +LibName13=xilinx +LibName14=microcontrollers +LibName15=dsp +LibName16=microchip +LibName17=analog_switches +LibName18=motorola +LibName19=texas +LibName20=intel +LibName21=audio +LibName22=interface +LibName23=digital-audio +LibName24=philips +LibName25=display +LibName26=cypress +LibName27=siliconi +LibName28=opto +LibName29=atmel +LibName30=contrib +LibName31=power +LibName32=device +LibName33=transistors +LibName34=conn +LibName35=linear +LibName36=regul +LibName37=74xx +LibName38=cmos4000 diff --git a/RLC/RLC.proj b/RLC/RLC.proj new file mode 100644 index 0000000..fc0e0de --- /dev/null +++ b/RLC/RLC.proj @@ -0,0 +1 @@ +schematicFile RLC.sch diff --git a/RLC/RLC.sch b/RLC/RLC.sch new file mode 100644 index 0000000..250e7da --- /dev/null +++ b/RLC/RLC.sch @@ -0,0 +1,167 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:RLC-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L R R1 +U 1 1 56C172A1 +P 4850 2700 +F 0 "R1" H 4900 2830 50 0000 C CNN +F 1 "1k" H 4900 2750 50 0000 C CNN +F 2 "" H 4900 2680 30 0000 C CNN +F 3 "" V 4900 2750 30 0000 C CNN + 1 4850 2700 + 1 0 0 -1 +$EndComp +$Comp +L L L1 +U 1 1 56C172D6 +P 3800 3200 +F 0 "L1" H 5750 3700 50 0000 C CNN +F 1 "2" H 5750 3850 50 0000 C CNN +F 2 "" V 5750 3750 60 0000 C CNN +F 3 "" V 5750 3750 60 0000 C CNN + 1 3800 3200 + 1 0 0 -1 +$EndComp +$Comp +L C C1 +U 1 1 56C17369 +P 6400 3350 +F 0 "C1" H 6425 3450 50 0000 L CNN +F 1 "0.5u" H 6425 3250 50 0000 L CNN +F 2 "" H 6438 3200 30 0000 C CNN +F 3 "" H 6400 3350 60 0000 C CNN + 1 6400 3350 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 56C173A6 +P 5400 3900 +F 0 "#PWR01" H 5400 3650 50 0001 C CNN +F 1 "GND" H 5400 3750 50 0000 C CNN +F 2 "" H 5400 3900 50 0000 C CNN +F 3 "" H 5400 3900 50 0000 C CNN + 1 5400 3900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4200 2850 4200 2650 +Wire Wire Line + 4200 2650 4750 2650 +Wire Wire Line + 5050 2650 5450 2650 +Wire Wire Line + 6050 2650 6400 2650 +Wire Wire Line + 6400 2650 6400 3200 +Wire Wire Line + 4200 3750 4200 3850 +Wire Wire Line + 4200 3850 6400 3850 +Wire Wire Line + 6400 3850 6400 3500 +Wire Wire Line + 5400 3900 5400 3850 +Connection ~ 5400 3850 +Text GLabel 4200 2500 0 60 Input ~ 0 +in +Text GLabel 6400 2500 2 60 Input ~ 0 +out +Wire Wire Line + 4200 2500 4250 2500 +Wire Wire Line + 4250 2450 4250 2650 +Connection ~ 4250 2650 +Wire Wire Line + 6400 2500 6350 2500 +Wire Wire Line + 6350 2450 6350 2650 +Connection ~ 6350 2650 +$Comp +L pwl v1 +U 1 1 56C17805 +P 4200 3300 +F 0 "v1" H 4000 3400 60 0000 C CNN +F 1 "pwl" H 3950 3250 60 0000 C CNN +F 2 "R1" H 3900 3300 60 0000 C CNN +F 3 "" H 4200 3300 60 0000 C CNN + 1 4200 3300 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U1 +U 1 1 56D46D52 +P 4250 2650 +F 0 "U1" H 4250 3150 60 0000 C CNN +F 1 "plot_v1" H 4450 3000 60 0000 C CNN +F 2 "" H 4250 2650 60 0000 C CNN +F 3 "" H 4250 2650 60 0000 C CNN + 1 4250 2650 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U2 +U 1 1 56D46D8A +P 6350 2650 +F 0 "U2" H 6350 3150 60 0000 C CNN +F 1 "plot_v1" H 6550 3000 60 0000 C CNN +F 2 "" H 6350 2650 60 0000 C CNN +F 3 "" H 6350 2650 60 0000 C CNN + 1 6350 2650 + 1 0 0 -1 +$EndComp +Connection ~ 4250 2500 +Connection ~ 6350 2500 +$EndSCHEMATC diff --git a/RLC/RLC_Previous_Values.xml b/RLC/RLC_Previous_Values.xml new file mode 100644 index 0000000..6c2cb3c --- /dev/null +++ b/RLC/RLC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">10</field1></v1><v1 name="Source type">pwl<field1 name="Enter in pwl format">0m 0 0.5m 5</field1></v1></source><model /><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/RLC/analysis b/RLC/analysis new file mode 100644 index 0000000..660a46c --- /dev/null +++ b/RLC/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/RLC/plot_data_i.txt b/RLC/plot_data_i.txt new file mode 100644 index 0000000..8477b86 --- /dev/null +++ b/RLC/plot_data_i.txt @@ -0,0 +1,149 @@ + * /home/fossee/esim-workspace/rlc/rlc.cir + Transient Analysis Thu Mar 3 22:39:44 2016 +-------------------------------------------------------------------------------- +Index time l1#branch v1#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 +1 5.000000e-06 1.246852e-07 -1.24685e-07 +2 5.280178e-06 1.320634e-07 -1.32063e-07 +3 5.840535e-06 1.476028e-07 -1.47603e-07 +4 6.961248e-06 1.833769e-07 -1.83377e-07 +5 9.202674e-06 2.736938e-07 -2.73694e-07 +6 1.368553e-05 5.292944e-07 -5.29294e-07 +7 2.194726e-05 1.261510e-06 -1.26151e-06 +8 3.309725e-05 2.784352e-06 -2.78435e-06 +9 5.067770e-05 6.424587e-06 -6.42459e-06 +10 7.587736e-05 1.426097e-05 -1.42610e-05 +11 1.148834e-04 3.237590e-05 -3.23759e-05 +12 1.725767e-04 7.216826e-05 -7.21683e-05 +13 2.611301e-04 1.621561e-04 -1.62156e-04 +14 3.948212e-04 3.596591e-04 -3.59659e-04 +15 5.000000e-04 5.629267e-04 -5.62927e-04 +16 5.207170e-04 6.061485e-04 -6.06149e-04 +17 5.621511e-04 6.911548e-04 -6.91155e-04 +18 6.450192e-04 8.523044e-04 -8.52304e-04 +19 8.107554e-04 1.137162e-03 -1.13716e-03 +20 1.142228e-03 1.548131e-03 -1.54813e-03 +21 1.805173e-03 1.756741e-03 -1.75674e-03 +22 2.654913e-03 1.127431e-03 -1.12743e-03 +23 3.388366e-03 2.317053e-04 -2.31705e-04 +24 4.128785e-03 -5.14398e-04 5.143982e-04 +25 4.865315e-03 -8.37744e-04 8.377443e-04 +26 5.803136e-03 -6.54850e-04 6.548505e-04 +27 6.562563e-03 -2.29095e-04 2.290949e-04 +28 7.307299e-03 1.685116e-04 -1.68512e-04 +29 8.047002e-03 3.831069e-04 -3.83107e-04 +30 8.863450e-03 3.700387e-04 -3.70039e-04 +31 9.692949e-03 1.776432e-04 -1.77643e-04 +32 1.044491e-02 -2.83752e-05 2.837525e-05 +33 1.120165e-02 -1.64572e-04 1.645722e-04 +34 1.194571e-02 -1.91652e-04 1.916518e-04 +35 1.315428e-02 -8.11456e-05 8.114557e-05 +36 1.399830e-02 2.851303e-05 -2.85130e-05 +37 1.472570e-02 8.566113e-05 -8.56611e-05 +38 1.545691e-02 9.243617e-05 -9.24362e-05 +39 1.639911e-02 4.813320e-05 -4.81332e-05 +40 1.717006e-02 -2.22220e-06 2.222197e-06 +41 1.795598e-02 -3.75374e-05 3.753745e-05 +42 1.869340e-02 -4.56103e-05 4.561034e-05 +43 1.983040e-02 -2.27428e-05 2.274282e-05 +44 2.065113e-02 3.044264e-06 -3.04426e-06 +45 2.138550e-02 1.858309e-05 -1.85831e-05 +46 2.211369e-02 2.220465e-05 -2.22046e-05 +47 2.325765e-02 1.081720e-05 -1.08172e-05 +48 2.408176e-02 -1.76689e-06 1.766892e-06 +49 2.481531e-02 -9.19225e-06 9.192253e-06 +50 2.554235e-02 -1.08051e-05 1.080515e-05 +51 2.670586e-02 -5.01696e-06 5.016961e-06 +52 2.753661e-02 1.130777e-06 -1.13078e-06 +53 2.826826e-02 4.607322e-06 -4.60732e-06 +54 2.899257e-02 5.250038e-06 -5.25004e-06 + +Index time l1#branch v1#branch +-------------------------------------------------------------------------------- +55 3.004490e-02 2.639137e-06 -2.63914e-06 +56 3.084399e-02 -2.75452e-07 2.754519e-07 +57 3.157887e-02 -2.10870e-06 2.108698e-06 +58 3.230912e-02 -2.56839e-06 2.568394e-06 +59 3.344169e-02 -1.30172e-06 1.301720e-06 +60 3.426136e-02 1.497049e-07 -1.49705e-07 +61 3.499634e-02 1.035243e-06 -1.03524e-06 +62 3.572540e-02 1.250528e-06 -1.25053e-06 +63 3.685635e-02 6.278617e-07 -6.27862e-07 +64 3.767593e-02 -7.85629e-08 7.856290e-08 +65 3.841057e-02 -5.07016e-07 5.070159e-07 +66 3.913921e-02 -6.08891e-07 6.088910e-07 +67 4.027743e-02 -3.00741e-07 3.007411e-07 +68 4.109953e-02 4.386510e-08 -4.38651e-08 +69 4.183359e-02 2.497445e-07 -2.49744e-07 +70 4.256137e-02 2.963873e-07 -2.96387e-07 +71 4.371328e-02 1.416025e-07 -1.41603e-07 +72 4.454012e-02 -2.66604e-08 2.666042e-08 +73 4.527292e-02 -1.24238e-07 1.242377e-07 +74 4.599888e-02 -1.44150e-07 1.441503e-07 +75 4.717900e-02 -6.42054e-08 6.420537e-08 +76 4.801520e-02 1.801739e-08 -1.80174e-08 +77 4.874505e-02 6.287078e-08 -6.28708e-08 +78 4.946683e-02 6.991626e-08 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2.347229e-11 +122 8.698005e-02 -2.53563e-11 2.535626e-11 +123 8.793781e-02 -1.30270e-11 1.302698e-11 +124 8.872308e-02 9.842751e-13 -9.84275e-13 +125 8.952274e-02 1.057610e-11 -1.05761e-11 +126 9.027227e-02 1.245148e-11 -1.24515e-11 +127 9.142818e-02 5.701134e-12 -5.70113e-12 +128 9.227784e-02 -1.50900e-12 1.508999e-12 +129 9.303547e-02 -5.48907e-12 5.489074e-12 +130 9.378558e-02 -5.98274e-12 5.982744e-12 +131 9.481077e-02 -2.82205e-12 2.822051e-12 +132 9.564777e-02 6.426477e-13 -6.42647e-13 +133 9.649598e-02 2.749097e-12 -2.74910e-12 +134 9.728418e-02 2.838942e-12 -2.83894e-12 +135 9.834546e-02 1.112755e-12 -1.11275e-12 +136 9.923645e-02 -6.04480e-13 6.044809e-13 +137 1.000000e-01 -1.39307e-12 1.393069e-12 diff --git a/RLC/plot_data_v.txt b/RLC/plot_data_v.txt new file mode 100644 index 0000000..6bce828 --- /dev/null +++ b/RLC/plot_data_v.txt @@ -0,0 +1,149 @@ + * /home/fossee/esim-workspace/rlc/rlc.cir + Transient Analysis Thu Mar 3 22:39:44 2016 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3.588553e+00 9.911244e-02 +15 5.000000e-04 5.000000e+00 4.437073e+00 1.961489e-01 +16 5.207170e-04 5.000000e+00 4.393851e+00 2.212641e-01 +17 5.621511e-04 5.000000e+00 4.308845e+00 2.750166e-01 +18 6.450192e-04 5.000000e+00 4.147696e+00 4.029202e-01 +19 8.107554e-04 5.000000e+00 3.862838e+00 7.326468e-01 +20 1.142228e-03 5.000000e+00 3.451869e+00 1.622748e+00 +21 1.805173e-03 5.000000e+00 3.243259e+00 3.813696e+00 +22 2.654913e-03 5.000000e+00 3.872569e+00 6.264494e+00 +23 3.388366e-03 5.000000e+00 4.768295e+00 7.261355e+00 +24 4.128785e-03 5.000000e+00 5.514398e+00 7.052044e+00 +25 4.865315e-03 5.000000e+00 5.837744e+00 6.056151e+00 +26 5.803136e-03 5.000000e+00 5.654850e+00 4.656364e+00 +27 6.562563e-03 5.000000e+00 5.229095e+00 3.985072e+00 +28 7.307299e-03 5.000000e+00 4.831488e+00 3.939953e+00 +29 8.047002e-03 5.000000e+00 4.616893e+00 4.347987e+00 +30 8.863450e-03 5.000000e+00 4.629961e+00 4.962892e+00 +31 9.692949e-03 5.000000e+00 4.822357e+00 5.417193e+00 +32 1.044491e-02 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5.000000e+00 5.000000e+00 5.000000e+00 +135 9.834546e-02 5.000000e+00 5.000000e+00 5.000000e+00 +136 9.923645e-02 5.000000e+00 5.000000e+00 5.000000e+00 +137 1.000000e-01 5.000000e+00 5.000000e+00 5.000000e+00 |