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-rw-r--r--Half_Adder/Half_Adder.cir4
-rw-r--r--Half_Adder/Half_Adder.cir.out2
-rw-r--r--Half_Adder/_saved_half_adder.sch154
-rw-r--r--Half_Adder/plot_data_i.txt8
-rw-r--r--Half_Adder/plot_data_v.txt8
5 files changed, 11 insertions, 165 deletions
diff --git a/Half_Adder/Half_Adder.cir b/Half_Adder/Half_Adder.cir
index 4658c5c..e0fc9a2 100644
--- a/Half_Adder/Half_Adder.cir
+++ b/Half_Adder/Half_Adder.cir
@@ -1,6 +1,6 @@
-* /home/fossee/UpdatedExamples/Half_Adder/Half_Adder.cir
+* /home/fossee/eSim-Workspace/Half_Adder/Half_Adder.cir
-* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Mar 3 21:35:33 2016
+* EESchema Netlist Version 1.1 (Spice format) creation date: Fri May 27 16:50:24 2016
* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
diff --git a/Half_Adder/Half_Adder.cir.out b/Half_Adder/Half_Adder.cir.out
index 96066ff..6b42572 100644
--- a/Half_Adder/Half_Adder.cir.out
+++ b/Half_Adder/Half_Adder.cir.out
@@ -1,4 +1,4 @@
-* /home/fossee/updatedexamples/half_adder/half_adder.cir
+* /home/fossee/esim-workspace/half_adder/half_adder.cir
.include half_adder.sub
x1 net-_u1-pad3_ net-_u1-pad4_ net-_u2-pad1_ net-_u2-pad2_ half_adder
diff --git a/Half_Adder/_saved_half_adder.sch b/Half_Adder/_saved_half_adder.sch
deleted file mode 100644
index d66359c..0000000
--- a/Half_Adder/_saved_half_adder.sch
+++ /dev/null
@@ -1,154 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:half_adder-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_xor U2
-U 1 1 558A946A
-P 5650 3050
-F 0 "U2" H 5650 3050 60 0000 C CNN
-F 1 "d_xor" H 5700 3150 47 0000 C CNN
-F 2 "" H 5650 3050 60 0000 C CNN
-F 3 "" H 5650 3050 60 0000 C CNN
- 1 5650 3050
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U3
-U 1 1 558A94D5
-P 5700 3800
-F 0 "U3" H 5700 3800 60 0000 C CNN
-F 1 "d_and" H 5750 3900 60 0000 C CNN
-F 2 "" H 5700 3800 60 0000 C CNN
-F 3 "" H 5700 3800 60 0000 C CNN
- 1 5700 3800
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 1 1 558A94F6
-P 4150 3000
-F 0 "U1" H 4200 3100 30 0000 C CNN
-F 1 "PORT" H 4150 3000 30 0000 C CNN
-F 2 "" H 4150 3000 60 0000 C CNN
-F 3 "" H 4150 3000 60 0000 C CNN
- 1 4150 3000
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 558A9543
-P 4150 3450
-F 0 "U1" H 4200 3550 30 0000 C CNN
-F 1 "PORT" H 4150 3450 30 0000 C CNN
-F 2 "" H 4150 3450 60 0000 C CNN
-F 3 "" H 4150 3450 60 0000 C CNN
- 2 4150 3450
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 558A9573
-P 6650 3000
-F 0 "U1" H 6700 3100 30 0000 C CNN
-F 1 "PORT" H 6650 3000 30 0000 C CNN
-F 2 "" H 6650 3000 60 0000 C CNN
-F 3 "" H 6650 3000 60 0000 C CNN
- 3 6650 3000
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 558A9606
-P 6700 3750
-F 0 "U1" H 6750 3850 30 0000 C CNN
-F 1 "PORT" H 6700 3750 30 0000 C CNN
-F 2 "" H 6700 3750 60 0000 C CNN
-F 3 "" H 6700 3750 60 0000 C CNN
- 4 6700 3750
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 5200 2950 4450 2950
-Wire Wire Line
- 4450 2950 4450 3000
-Wire Wire Line
- 4450 3000 4400 3000
-Wire Wire Line
- 4400 3450 4550 3450
-Wire Wire Line
- 4550 3450 4550 3050
-Wire Wire Line
- 4550 3050 5200 3050
-Wire Wire Line
- 5250 3700 5000 3700
-Wire Wire Line
- 5000 3700 5000 2950
-Connection ~ 5000 2950
-Wire Wire Line
- 5250 3800 4850 3800
-Wire Wire Line
- 4850 3800 4850 3050
-Connection ~ 4850 3050
-Wire Wire Line
- 6100 3000 6400 3000
-Wire Wire Line
- 6150 3750 6450 3750
-Text Notes 4550 2950 0 60 ~ 0
-IN1\n\n
-Text Notes 4600 3150 0 60 ~ 0
-IN2
-Text Notes 6200 2950 0 60 ~ 0
-SUM\n
-Text Notes 6200 3650 0 60 ~ 0
-COUT\n
-$EndSCHEMATC
diff --git a/Half_Adder/plot_data_i.txt b/Half_Adder/plot_data_i.txt
index 772acd2..5f03498 100644
--- a/Half_Adder/plot_data_i.txt
+++ b/Half_Adder/plot_data_i.txt
@@ -1,5 +1,5 @@
- * /home/fossee/updatedexamples/half_adder/half_adder.cir
- Transient Analysis Thu Mar 3 21:35:49 2016
+ * /home/fossee/esim-workspace/half_adder/half_adder.cir
+ Transient Analysis Fri May 27 16:50:38 2016
--------------------------------------------------------------------------------
Index time a2#branch_1_0 a2#branch_1_1 v1#branch
--------------------------------------------------------------------------------
@@ -66,8 +66,8 @@ Index time a2#branch_1_0 a2#branch_1_1 v1#branch
57 9.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
58 1.000000e-01 -5.00000e-03 0.000000e+00 0.000000e+00
- * /home/fossee/updatedexamples/half_adder/half_adder.cir
- Transient Analysis Thu Mar 3 21:35:49 2016
+ * /home/fossee/esim-workspace/half_adder/half_adder.cir
+ Transient Analysis Fri May 27 16:50:38 2016
--------------------------------------------------------------------------------
Index time v2#branch
--------------------------------------------------------------------------------
diff --git a/Half_Adder/plot_data_v.txt b/Half_Adder/plot_data_v.txt
index f970ecb..7dea4a7 100644
--- a/Half_Adder/plot_data_v.txt
+++ b/Half_Adder/plot_data_v.txt
@@ -1,5 +1,5 @@
- * /home/fossee/updatedexamples/half_adder/half_adder.cir
- Transient Analysis Thu Mar 3 21:35:49 2016
+ * /home/fossee/esim-workspace/half_adder/half_adder.cir
+ Transient Analysis Fri May 27 16:50:38 2016
--------------------------------------------------------------------------------
Index time cout in1 in2
--------------------------------------------------------------------------------
@@ -66,8 +66,8 @@ Index time cout in1 in2
57 9.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00
58 1.000000e-01 0.000000e+00 5.000000e+00 0.000000e+00
- * /home/fossee/updatedexamples/half_adder/half_adder.cir
- Transient Analysis Thu Mar 3 21:35:49 2016
+ * /home/fossee/esim-workspace/half_adder/half_adder.cir
+ Transient Analysis Fri May 27 16:50:38 2016
--------------------------------------------------------------------------------
Index time sum
--------------------------------------------------------------------------------
generated by cgit (git 2.34.1) at 2025-04-01 00:41:08 +0000