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| author | fahimkhan | 2016-03-14 16:37:03 +0530 |
|---|---|---|
| committer | fahimkhan | 2016-03-14 16:37:03 +0530 |
| commit | 0767e64446641553c7c08c77b53d4817599c4ae1 (patch) | |
| tree | ccc60cf033e7d1f56fe52633462c9e659de8af1d /Diac_Triac/diac.sub | |
| parent | 9182fa7645ca28bd5d2d8401c2e2f03c39943f92 (diff) | |
| download | eSim-Examples-0767e64446641553c7c08c77b53d4817599c4ae1.tar.gz eSim-Examples-0767e64446641553c7c08c77b53d4817599c4ae1.tar.bz2 eSim-Examples-0767e64446641553c7c08c77b53d4817599c4ae1.zip | |
Adding all available eSim examples
Diffstat (limited to 'Diac_Triac/diac.sub')
| -rw-r--r-- | Diac_Triac/diac.sub | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/Diac_Triac/diac.sub b/Diac_Triac/diac.sub new file mode 100644 index 0000000..7f28ecc --- /dev/null +++ b/Diac_Triac/diac.sub @@ -0,0 +1,15 @@ +* Subcircuit diac +.subckt diac 1 2 +* /opt/esim/src/subcircuitlibrary/diac/diac.cir +* u1 1 1 2 aswitch +* u2 1 1 2 aswitch +a1 1 (1 2) u1 +a2 1 (1 2) u2 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) + +* Control Statements + +.ends diac |