diff options
Diffstat (limited to 'digital ciruits/cmos_nand_sub')
| -rw-r--r-- | digital ciruits/cmos_nand_sub/cmos_nand_sub-cache.lib | 82 | ||||
| -rw-r--r-- | digital ciruits/cmos_nand_sub/cmos_nand_sub.bak | 186 | ||||
| -rw-r--r-- | digital ciruits/cmos_nand_sub/cmos_nand_sub.cir | 13 | ||||
| -rw-r--r-- | digital ciruits/cmos_nand_sub/cmos_nand_sub.pro | 33 | ||||
| -rw-r--r-- | digital ciruits/cmos_nand_sub/cmos_nand_sub.sch | 203 | ||||
| -rw-r--r-- | digital ciruits/cmos_nand_sub/sym-lib-table | 3 |
6 files changed, 520 insertions, 0 deletions
diff --git a/digital ciruits/cmos_nand_sub/cmos_nand_sub-cache.lib b/digital ciruits/cmos_nand_sub/cmos_nand_sub-cache.lib new file mode 100644 index 0000000..d0e6eb2 --- /dev/null +++ b/digital ciruits/cmos_nand_sub/cmos_nand_sub-cache.lib @@ -0,0 +1,82 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:VDD +# +DEF power:VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power:VDD" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:0 +# +DEF pspice:0 #GND 0 0 Y Y 1 F P +F0 "#GND" 0 -100 50 H I C CNN +F1 "pspice:0" 0 -70 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X 0 1 0 0 0 R 40 40 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# sim_logic:CMOS_NAND +# +DEF sim_logic:CMOS_NAND X 0 20 Y Y 1 F N +F0 "X" 0 -400 50 H V C CNN +F1 "sim_logic:CMOS_NAND" 0 -300 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +A 200 0 200 -899 899 0 1 0 N 200 -200 200 200 +P 4 0 1 0 200 200 0 200 0 -200 200 -200 N +X A A -200 100 200 R 50 50 1 1 I +X B B -200 -100 200 R 50 50 1 1 I +X Out Out 600 0 200 L 50 50 1 1 O I +X VDD VDD 200 400 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/cmos_nand_sub/cmos_nand_sub.bak b/digital ciruits/cmos_nand_sub/cmos_nand_sub.bak new file mode 100644 index 0000000..3be2dcc --- /dev/null +++ b/digital ciruits/cmos_nand_sub/cmos_nand_sub.bak @@ -0,0 +1,186 @@ +EESchema Schematic File Version 4 +LIBS:cmos_nand_sub-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:0 #GND01 +U 1 1 5B1AEE1C +P 1400 3800 +F 0 "#GND01" H 1400 3700 50 0001 C CNN +F 1 "0" H 1400 3887 50 0000 C CNN +F 2 "" H 1400 3800 50 0001 C CNN +F 3 "" H 1400 3800 50 0001 C CNN + 1 1400 3800 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V1 +U 1 1 5B1AEF25 +P 1400 3050 +F 0 "V1" H 1828 3096 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1828 3005 50 0000 L CNN +F 2 "" H 1400 3050 50 0001 C CNN +F 3 "" H 1400 3050 50 0001 C CNN +F 4 "V" H 1400 3050 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1400 3050 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 3050 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 3800 1400 3750 +Text GLabel 5300 3250 0 50 Input ~ 0 +A +$Comp +L pspice:VSOURCE V2 +U 1 1 5B1B81D1 +P 10200 3800 +F 0 "V2" H 10628 3846 50 0000 L CNN +F 1 "3.3" H 10628 3755 50 0000 L CNN +F 2 "" H 10200 3800 50 0001 C CNN +F 3 "" H 10200 3800 50 0001 C CNN + 1 10200 3800 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR01 +U 1 1 5B1B83AE +P 10200 3100 +F 0 "#PWR01" H 10200 2950 50 0001 C CNN +F 1 "VDD" H 10217 3273 50 0000 C CNN +F 2 "" H 10200 3100 50 0001 C CNN +F 3 "" H 10200 3100 50 0001 C CNN + 1 10200 3100 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR02 +U 1 1 5B1B83E5 +P 5700 2950 +F 0 "#PWR02" H 5700 2800 50 0001 C CNN +F 1 "VDD" H 5717 3123 50 0000 C CNN +F 2 "" H 5700 2950 50 0001 C CNN +F 3 "" H 5700 2950 50 0001 C CNN + 1 5700 2950 + 1 0 0 -1 +$EndComp +Text Notes 1000 1100 0 80 ~ 0 +A NAND gate implemented using MOSFETs\n\nfrom https://en.wikipedia.org/wiki/CMOS +Wire Wire Line + 1400 2250 1400 2350 +Text Notes 5350 4700 0 50 ~ 0 +.tran 1m 400m +Text Notes 9900 4850 0 50 ~ 0 +Supply voltage +Text Notes 1000 1600 0 50 ~ 0 +Notes:\n\n1. the dotted section implements a 2-input NAND gate using PMOS/NMOS pair\n2. In ngspice it is implemented as a subcircuit\n3. Run the simulation and plot V(A), V(B) and V(out) +Text GLabel 1500 2250 2 50 Output ~ 0 +A +Text GLabel 1500 4200 2 50 Output ~ 0 +B +Text GLabel 5300 3450 0 50 Input ~ 0 +B +$Comp +L pspice:0 #GND04 +U 1 1 5B24BFD8 +P 10200 4500 +F 0 "#GND04" H 10200 4400 50 0001 C CNN +F 1 "0" H 10200 4587 50 0000 C CNN +F 2 "" H 10200 4500 50 0001 C CNN +F 3 "" H 10200 4500 50 0001 C CNN + 1 10200 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 2250 1500 2250 +$Comp +L pspice:0 #GND02 +U 1 1 5B24F37F +P 1400 5750 +F 0 "#GND02" H 1400 5650 50 0001 C CNN +F 1 "0" H 1400 5837 50 0000 C CNN +F 2 "" H 1400 5750 50 0001 C CNN +F 3 "" H 1400 5750 50 0001 C CNN + 1 1400 5750 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B24F388 +P 1400 5000 +F 0 "V3" H 1828 5046 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 0 0 0 50m 100m)" H 1828 4955 50 0000 L CNN +F 2 "" H 1400 5000 50 0001 C CNN +F 3 "" H 1400 5000 50 0001 C CNN +F 4 "V" H 1400 5000 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 50m 100m)" H 1400 5000 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 5000 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 5000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 5750 1400 5700 +Wire Wire Line + 1400 4200 1400 4300 +Wire Wire Line + 1400 4200 1500 4200 +Text Notes 1150 6050 0 50 ~ 0 +Test input signals +Text Notes 5350 5250 0 50 ~ 0 +.control\nrun\nplot v(a)+5 v(b)+10 v(out)\n.endc +$Comp +L sim_logic:CMOS_NAND X1 +U 1 1 5B25203E +P 5500 3350 +F 0 "X1" H 5700 3078 50 0000 C CNN +F 1 "CMOS_NAND" H 5700 2987 50 0000 C CNN +F 2 "" H 5500 3350 50 0001 C CNN +F 3 "" H 5500 3350 50 0001 C CNN +F 4 "X" H 5500 3350 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 5500 3350 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5500 3350 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 5500 3350 50 0001 C CNN "Spice_Lib_File" + 1 5500 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6750 3350 6100 3350 +Text GLabel 6500 3350 0 50 BiDi ~ 0 +Out +$Comp +L device:R R1 +U 1 1 5B2526A7 +P 6750 3500 +F 0 "R1" H 6820 3546 50 0000 L CNN +F 1 "10meg" H 6820 3455 50 0000 L CNN +F 2 "" V 6680 3500 50 0001 C CNN +F 3 "" H 6750 3500 50 0001 C CNN + 1 6750 3500 + 1 0 0 -1 +$EndComp +$Comp +L pspice:0 #GND03 +U 1 1 5B2526F1 +P 6750 3800 +F 0 "#GND03" H 6750 3700 50 0001 C CNN +F 1 "0" H 6750 3887 50 0000 C CNN +F 2 "" H 6750 3800 50 0001 C CNN +F 3 "" H 6750 3800 50 0001 C CNN + 1 6750 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6750 3650 6750 3800 +$EndSCHEMATC diff --git a/digital ciruits/cmos_nand_sub/cmos_nand_sub.cir b/digital ciruits/cmos_nand_sub/cmos_nand_sub.cir new file mode 100644 index 0000000..de057ba --- /dev/null +++ b/digital ciruits/cmos_nand_sub/cmos_nand_sub.cir @@ -0,0 +1,13 @@ +.title KiCad schematic +.include "../libs/spice_models.lib" +V1 A 0 dc 0 pulse(0 3.3 0 0 0 100m 200m) +V2 VDD 0 3.3 +V3 B 0 dc 0 pulse(0 3.3 0 0 0 50m 100m) +X1 A B Out VDD NAND +R1 0 Out 10meg +.tran 1m 400m +.control +run +plot v(a)+5 v(b)+10 v(out) +.endc +.end diff --git a/digital ciruits/cmos_nand_sub/cmos_nand_sub.pro b/digital ciruits/cmos_nand_sub/cmos_nand_sub.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/digital ciruits/cmos_nand_sub/cmos_nand_sub.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/digital ciruits/cmos_nand_sub/cmos_nand_sub.sch b/digital ciruits/cmos_nand_sub/cmos_nand_sub.sch new file mode 100644 index 0000000..50cb360 --- /dev/null +++ b/digital ciruits/cmos_nand_sub/cmos_nand_sub.sch @@ -0,0 +1,203 @@ +EESchema Schematic File Version 4 +LIBS:cmos_nand_sub-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:0 #GND01 +U 1 1 5B1AEE1C +P 1400 3800 +F 0 "#GND01" H 1400 3700 50 0001 C CNN +F 1 "0" H 1400 3887 50 0000 C CNN +F 2 "" H 1400 3800 50 0001 C CNN +F 3 "" H 1400 3800 50 0001 C CNN + 1 1400 3800 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V1 +U 1 1 5B1AEF25 +P 1400 3050 +F 0 "V1" H 1828 3096 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1828 3005 50 0000 L CNN +F 2 "" H 1400 3050 50 0001 C CNN +F 3 "" H 1400 3050 50 0001 C CNN +F 4 "V" H 1400 3050 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1400 3050 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 3050 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 3050 + 1 0 0 -1 +$EndComp +Text GLabel 5300 3250 0 50 Input ~ 0 +A +$Comp +L pspice:VSOURCE V2 +U 1 1 5B1B81D1 +P 10200 3800 +F 0 "V2" H 10628 3846 50 0000 L CNN +F 1 "3.3" H 10628 3755 50 0000 L CNN +F 2 "" H 10200 3800 50 0001 C CNN +F 3 "" H 10200 3800 50 0001 C CNN + 1 10200 3800 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR01 +U 1 1 5B1B83AE +P 10200 3100 +F 0 "#PWR01" H 10200 2950 50 0001 C CNN +F 1 "VDD" H 10217 3273 50 0000 C CNN +F 2 "" H 10200 3100 50 0001 C CNN +F 3 "" H 10200 3100 50 0001 C CNN + 1 10200 3100 + 1 0 0 -1 +$EndComp +$Comp +L power:VDD #PWR02 +U 1 1 5B1B83E5 +P 5700 2950 +F 0 "#PWR02" H 5700 2800 50 0001 C CNN +F 1 "VDD" H 5717 3123 50 0000 C CNN +F 2 "" H 5700 2950 50 0001 C CNN +F 3 "" H 5700 2950 50 0001 C CNN + 1 5700 2950 + 1 0 0 -1 +$EndComp +Text Notes 1000 1100 0 80 ~ 0 +A NAND gate implemented using MOSFETs\n\nfrom https://en.wikipedia.org/wiki/CMOS +Text Notes 5350 4700 0 50 ~ 0 +.tran 1m 400m +Text Notes 9900 4850 0 50 ~ 0 +Supply voltage +Text Notes 1000 1600 0 50 ~ 0 +Notes:\n\n1. the dotted section implements a 2-input NAND gate using PMOS/NMOS pair\n2. In ngspice it is implemented as a subcircuit\n3. Run the simulation and plot V(A), V(B) and V(out) +Text GLabel 1500 2250 2 50 Output ~ 0 +A +Text GLabel 1500 4200 2 50 Output ~ 0 +B +Text GLabel 5300 3450 0 50 Input ~ 0 +B +$Comp +L pspice:0 #GND04 +U 1 1 5B24BFD8 +P 10200 4500 +F 0 "#GND04" H 10200 4400 50 0001 C CNN +F 1 "0" H 10200 4587 50 0000 C CNN +F 2 "" H 10200 4500 50 0001 C CNN +F 3 "" H 10200 4500 50 0001 C CNN + 1 10200 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 2250 1500 2250 +$Comp +L pspice:0 #GND02 +U 1 1 5B24F37F +P 1400 5750 +F 0 "#GND02" H 1400 5650 50 0001 C CNN +F 1 "0" H 1400 5837 50 0000 C CNN +F 2 "" H 1400 5750 50 0001 C CNN +F 3 "" H 1400 5750 50 0001 C CNN + 1 1400 5750 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V3 +U 1 1 5B24F388 +P 1400 5000 +F 0 "V3" H 1828 5046 50 0000 L CNN +F 1 "dc 0 pulse(0 3.3 0 0 0 50m 100m)" H 1828 4955 50 0000 L CNN +F 2 "" H 1400 5000 50 0001 C CNN +F 3 "" H 1400 5000 50 0001 C CNN +F 4 "V" H 1400 5000 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 50m 100m)" H 1400 5000 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1400 5000 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1400 5000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 4200 1500 4200 +Text Notes 1150 6050 0 50 ~ 0 +Test input signals +Text Notes 5350 5250 0 50 ~ 0 +.control\nrun\nplot v(a)+5 v(b)+10 v(out)\n.endc +$Comp +L sim_logic:CMOS_NAND X1 +U 1 1 5B25203E +P 5500 3350 +F 0 "X1" H 5700 3078 50 0000 C CNN +F 1 "CMOS_NAND" H 5700 2987 50 0000 C CNN +F 2 "" H 5500 3350 50 0001 C CNN +F 3 "" H 5500 3350 50 0001 C CNN +F 4 "X" H 5500 3350 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 5500 3350 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5500 3350 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "../libs/spice_models.lib" H 5500 3350 50 0001 C CNN "Spice_Lib_File" + 1 5500 3350 + 1 0 0 -1 +$EndComp +Text GLabel 6300 2850 0 50 BiDi ~ 0 +Out +$Comp +L pspice:0 #GND03 +U 1 1 5B2526F1 +P 6750 3800 +F 0 "#GND03" H 6750 3700 50 0001 C CNN +F 1 "0" H 6750 3887 50 0000 C CNN +F 2 "" H 6750 3800 50 0001 C CNN +F 3 "" H 6750 3800 50 0001 C CNN + 1 6750 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6750 3650 6750 3800 +Wire Wire Line + 1400 2250 1400 2750 +Wire Wire Line + 1400 3350 1400 3800 +Wire Wire Line + 1400 4200 1400 4700 +Wire Wire Line + 1400 5300 1400 5750 +Wire Wire Line + 10200 3500 10200 3100 +Wire Wire Line + 10200 4100 10200 4500 +$Comp +L Device:R R1 +U 1 1 5B324889 +P 7300 3400 +F 0 "R1" V 7093 3400 50 0000 C CNN +F 1 "10meg" V 7184 3400 50 0000 C CNN +F 2 "" V 7230 3400 50 0001 C CNN +F 3 "~" H 7300 3400 50 0001 C CNN + 1 7300 3400 + 0 1 1 0 +$EndComp +Wire Wire Line + 7150 3350 7150 3400 +Wire Wire Line + 6100 3350 6700 3350 +Wire Wire Line + 7450 3400 7450 3650 +Wire Wire Line + 7450 3650 6750 3650 +Wire Wire Line + 6300 2850 6700 2850 +Wire Wire Line + 6700 2850 6700 3350 +Connection ~ 6700 3350 +Wire Wire Line + 6700 3350 7150 3350 +$EndSCHEMATC diff --git a/digital ciruits/cmos_nand_sub/sym-lib-table b/digital ciruits/cmos_nand_sub/sym-lib-table new file mode 100644 index 0000000..63105ad --- /dev/null +++ b/digital ciruits/cmos_nand_sub/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name sim_logic)(type Legacy)(uri ${KIPRJMOD}/../libs/sim_logic.lib)(options "")(descr "")) +) |