diff options
Diffstat (limited to 'digital ciruits/and_sub')
| -rw-r--r-- | digital ciruits/and_sub/and_sub-cache.lib | 70 | ||||
| -rw-r--r-- | digital ciruits/and_sub/and_sub.bak | 185 | ||||
| -rw-r--r-- | digital ciruits/and_sub/and_sub.cir | 9 | ||||
| -rw-r--r-- | digital ciruits/and_sub/and_sub.kicad_pcb | 1 | ||||
| -rw-r--r-- | digital ciruits/and_sub/and_sub.pro | 33 | ||||
| -rw-r--r-- | digital ciruits/and_sub/and_sub.sch | 186 | ||||
| -rw-r--r-- | digital ciruits/and_sub/b3v33check.log | 4 | ||||
| -rw-r--r-- | digital ciruits/and_sub/basic_gates.bck | 3 | ||||
| -rw-r--r-- | digital ciruits/and_sub/basic_gates.dcm | 3 | ||||
| -rw-r--r-- | digital ciruits/and_sub/basic_gates.lib | 56 | ||||
| -rw-r--r-- | digital ciruits/and_sub/sym-lib-table | 3 |
11 files changed, 553 insertions, 0 deletions
diff --git a/digital ciruits/and_sub/and_sub-cache.lib b/digital ciruits/and_sub/and_sub-cache.lib new file mode 100644 index 0000000..7e993b2 --- /dev/null +++ b/digital ciruits/and_sub/and_sub-cache.lib @@ -0,0 +1,70 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# basic_gates:and +# +DEF basic_gates:and X 0 40 Y Y 1 F N +F0 "X" 0 250 50 H V C CNN +F1 "basic_gates:and" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +A 250 0 206 760 -760 0 1 0 N 300 200 300 -200 +P 2 0 1 0 -350 -200 300 -200 N +P 2 0 1 0 -350 200 -350 -200 N +P 2 0 1 0 -350 200 300 200 N +X A 1 -450 100 100 R 50 50 1 1 I +X B 2 -450 -100 100 R 50 50 1 1 I +X Out 3 550 0 100 L 50 50 1 1 O +X VDD 4 150 300 100 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/and_sub/and_sub.bak b/digital ciruits/and_sub/and_sub.bak new file mode 100644 index 0000000..e3fb14a --- /dev/null +++ b/digital ciruits/and_sub/and_sub.bak @@ -0,0 +1,185 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L basic_gates:and X1 +U 1 1 5B28C859 +P 5550 3900 +F 0 "X1" H 5600 3628 50 0000 C CNN +F 1 "and" H 5600 3537 50 0000 C CNN +F 2 "" H 5550 3900 50 0001 C CNN +F 3 "" H 5550 3900 50 0001 C CNN +F 4 "X" H 5550 3900 50 0001 C CNN "Spice_Primitive" +F 5 "AND" H 5550 3900 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5550 3900 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 5550 3900 50 0001 C CNN "Spice_Lib_File" + 1 5550 3900 + 1 0 0 -1 +$EndComp +Text GLabel 4200 3800 0 50 Input ~ 0 +a +Wire Wire Line + 4200 3800 5100 3800 +Text GLabel 4200 4000 0 50 Input ~ 0 +b +Wire Wire Line + 4200 4000 5100 4000 +$Comp +L Device:R R1 +U 1 1 5B28C8FD +P 7400 3850 +F 0 "R1" V 7193 3850 50 0000 C CNN +F 1 "10meg" V 7284 3850 50 0000 C CNN +F 2 "" V 7330 3850 50 0001 C CNN +F 3 "~" H 7400 3850 50 0001 C CNN + 1 7400 3850 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR04 +U 1 1 5B28C98E +P 7700 4150 +F 0 "#PWR04" H 7700 3900 50 0001 C CNN +F 1 "GND" H 7705 3977 50 0000 C CNN +F 2 "" H 7700 4150 50 0001 C CNN +F 3 "" H 7700 4150 50 0001 C CNN + 1 7700 4150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7700 4150 7700 3850 +Wire Wire Line + 7700 3850 7550 3850 +Wire Wire Line + 7250 3850 7000 3850 +Wire Wire Line + 6100 3850 6100 3900 +Text GLabel 6750 3350 0 50 Output ~ 0 +out +Wire Wire Line + 6750 3350 7000 3350 +Wire Wire Line + 7000 3350 7000 3850 +Connection ~ 7000 3850 +Wire Wire Line + 7000 3850 6100 3850 +Text GLabel 5400 3050 0 50 Input ~ 0 +vdd +Wire Wire Line + 5400 3050 5700 3050 +Wire Wire Line + 5700 3050 5700 3600 +$Comp +L pspice:VSOURCE V1 +U 1 1 5B28CB23 +P 2350 3650 +F 0 "V1" H 2578 3696 50 0000 L CNN +F 1 "VSOURCE" H 2578 3605 50 0000 L CNN +F 2 "" H 2350 3650 50 0001 C CNN +F 3 "" H 2350 3650 50 0001 C CNN +F 4 "V" H 2350 3650 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 2350 3650 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2350 3650 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2350 3650 + 1 0 0 -1 +$EndComp +Text GLabel 2150 3050 0 50 Input ~ 0 +a +$Comp +L power:GND #PWR01 +U 1 1 5B28CB63 +P 2350 4150 +F 0 "#PWR01" H 2350 3900 50 0001 C CNN +F 1 "GND" H 2355 3977 50 0000 C CNN +F 2 "" H 2350 4150 50 0001 C CNN +F 3 "" H 2350 4150 50 0001 C CNN + 1 2350 4150 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V2 +U 1 1 5B28CB77 +P 2350 5050 +F 0 "V2" H 2578 5096 50 0000 L CNN +F 1 "VSOURCE" H 2578 5005 50 0000 L CNN +F 2 "" H 2350 5050 50 0001 C CNN +F 3 "" H 2350 5050 50 0001 C CNN +F 4 "V" H 2350 5050 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 50m 0 0 50m 100m)" H 2350 5050 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2350 5050 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2350 5050 + 1 0 0 -1 +$EndComp +Text GLabel 2250 4600 0 50 Input ~ 0 +b +$Comp +L power:GND #PWR02 +U 1 1 5B28CBDF +P 2350 5550 +F 0 "#PWR02" H 2350 5300 50 0001 C CNN +F 1 "GND" H 2355 5377 50 0000 C CNN +F 2 "" H 2350 5550 50 0001 C CNN +F 3 "" H 2350 5550 50 0001 C CNN + 1 2350 5550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2150 3050 2350 3050 +Wire Wire Line + 2350 3050 2350 3350 +Wire Wire Line + 2350 4150 2350 3950 +Wire Wire Line + 2250 4600 2350 4600 +Wire Wire Line + 2350 4600 2350 4750 +Wire Wire Line + 2350 5350 2350 5550 +$Comp +L pspice:VSOURCE V3 +U 1 1 5B28D002 +P 5300 5300 +F 0 "V3" H 5528 5346 50 0000 L CNN +F 1 "VSOURCE" H 5528 5255 50 0000 L CNN +F 2 "" H 5300 5300 50 0001 C CNN +F 3 "" H 5300 5300 50 0001 C CNN +F 4 "V" H 5300 5300 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 5300 5300 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5300 5300 50 0001 C CNN "Spice_Netlist_Enabled" + 1 5300 5300 + 1 0 0 -1 +$EndComp +Text GLabel 5100 4700 0 50 Input ~ 0 +vdd +$Comp +L power:GND #PWR03 +U 1 1 5B28D086 +P 5300 5800 +F 0 "#PWR03" H 5300 5550 50 0001 C CNN +F 1 "GND" H 5305 5627 50 0000 C CNN +F 2 "" H 5300 5800 50 0001 C CNN +F 3 "" H 5300 5800 50 0001 C CNN + 1 5300 5800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 4700 5300 4700 +Wire Wire Line + 5300 4700 5300 5000 +Wire Wire Line + 5300 5600 5300 5800 +Text Notes 7500 5550 0 50 ~ 0 +.tran 1m 400m +$EndSCHEMATC diff --git a/digital ciruits/and_sub/and_sub.cir b/digital ciruits/and_sub/and_sub.cir new file mode 100644 index 0000000..2e3875e --- /dev/null +++ b/digital ciruits/and_sub/and_sub.cir @@ -0,0 +1,9 @@ +.title KiCad schematic +.include "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" +X1 a b out vdd AND +R1 GND out 10meg +V1 a GND dc 0 pulse(0 3.3 0 0 0 100m 200m) +V2 b GND dc 0 pulse(0 3.3 50m 0 0 50m 100m) +V3 vdd GND dc 3.3 +.tran 1m 400m +.end diff --git a/digital ciruits/and_sub/and_sub.kicad_pcb b/digital ciruits/and_sub/and_sub.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/digital ciruits/and_sub/and_sub.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/digital ciruits/and_sub/and_sub.pro b/digital ciruits/and_sub/and_sub.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/digital ciruits/and_sub/and_sub.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/digital ciruits/and_sub/and_sub.sch b/digital ciruits/and_sub/and_sub.sch new file mode 100644 index 0000000..bebf8ba --- /dev/null +++ b/digital ciruits/and_sub/and_sub.sch @@ -0,0 +1,186 @@ +EESchema Schematic File Version 4 +LIBS:and_sub-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L basic_gates:and X1 +U 1 1 5B28C859 +P 5550 3900 +F 0 "X1" H 5600 3628 50 0000 C CNN +F 1 "and" H 5600 3537 50 0000 C CNN +F 2 "" H 5550 3900 50 0001 C CNN +F 3 "" H 5550 3900 50 0001 C CNN +F 4 "X" H 5550 3900 50 0001 C CNN "Spice_Primitive" +F 5 "AND" H 5550 3900 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5550 3900 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 5550 3900 50 0001 C CNN "Spice_Lib_File" + 1 5550 3900 + 1 0 0 -1 +$EndComp +Text GLabel 4200 3800 0 50 Input ~ 0 +a +Wire Wire Line + 4200 3800 5100 3800 +Text GLabel 4200 4000 0 50 Input ~ 0 +b +Wire Wire Line + 4200 4000 5100 4000 +$Comp +L Device:R R1 +U 1 1 5B28C8FD +P 7400 3850 +F 0 "R1" V 7193 3850 50 0000 C CNN +F 1 "10meg" V 7284 3850 50 0000 C CNN +F 2 "" V 7330 3850 50 0001 C CNN +F 3 "~" H 7400 3850 50 0001 C CNN + 1 7400 3850 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR04 +U 1 1 5B28C98E +P 7700 4150 +F 0 "#PWR04" H 7700 3900 50 0001 C CNN +F 1 "GND" H 7705 3977 50 0000 C CNN +F 2 "" H 7700 4150 50 0001 C CNN +F 3 "" H 7700 4150 50 0001 C CNN + 1 7700 4150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7700 4150 7700 3850 +Wire Wire Line + 7700 3850 7550 3850 +Wire Wire Line + 7250 3850 7000 3850 +Wire Wire Line + 6100 3850 6100 3900 +Text GLabel 6750 3350 0 50 Output ~ 0 +out +Wire Wire Line + 6750 3350 7000 3350 +Wire Wire Line + 7000 3350 7000 3850 +Connection ~ 7000 3850 +Wire Wire Line + 7000 3850 6100 3850 +Text GLabel 5400 3050 0 50 Input ~ 0 +vdd +Wire Wire Line + 5400 3050 5700 3050 +Wire Wire Line + 5700 3050 5700 3600 +$Comp +L pspice:VSOURCE V1 +U 1 1 5B28CB23 +P 2350 3650 +F 0 "V1" H 2578 3696 50 0000 L CNN +F 1 "VSOURCE" H 2578 3605 50 0000 L CNN +F 2 "" H 2350 3650 50 0001 C CNN +F 3 "" H 2350 3650 50 0001 C CNN +F 4 "V" H 2350 3650 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 2350 3650 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2350 3650 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2350 3650 + 1 0 0 -1 +$EndComp +Text GLabel 2150 3050 0 50 Input ~ 0 +a +$Comp +L power:GND #PWR01 +U 1 1 5B28CB63 +P 2350 4150 +F 0 "#PWR01" H 2350 3900 50 0001 C CNN +F 1 "GND" H 2355 3977 50 0000 C CNN +F 2 "" H 2350 4150 50 0001 C CNN +F 3 "" H 2350 4150 50 0001 C CNN + 1 2350 4150 + 1 0 0 -1 +$EndComp +$Comp +L pspice:VSOURCE V2 +U 1 1 5B28CB77 +P 2350 5050 +F 0 "V2" H 2578 5096 50 0000 L CNN +F 1 "VSOURCE" H 2578 5005 50 0000 L CNN +F 2 "" H 2350 5050 50 0001 C CNN +F 3 "" H 2350 5050 50 0001 C CNN +F 4 "V" H 2350 5050 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 50m 0 0 50m 100m)" H 2350 5050 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2350 5050 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2350 5050 + 1 0 0 -1 +$EndComp +Text GLabel 2250 4600 0 50 Input ~ 0 +b +$Comp +L power:GND #PWR02 +U 1 1 5B28CBDF +P 2350 5550 +F 0 "#PWR02" H 2350 5300 50 0001 C CNN +F 1 "GND" H 2355 5377 50 0000 C CNN +F 2 "" H 2350 5550 50 0001 C CNN +F 3 "" H 2350 5550 50 0001 C CNN + 1 2350 5550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2150 3050 2350 3050 +Wire Wire Line + 2350 3050 2350 3350 +Wire Wire Line + 2350 4150 2350 3950 +Wire Wire Line + 2250 4600 2350 4600 +Wire Wire Line + 2350 4600 2350 4750 +Wire Wire Line + 2350 5350 2350 5550 +$Comp +L pspice:VSOURCE V3 +U 1 1 5B28D002 +P 5300 5300 +F 0 "V3" H 5528 5346 50 0000 L CNN +F 1 "VSOURCE" H 5528 5255 50 0000 L CNN +F 2 "" H 5300 5300 50 0001 C CNN +F 3 "" H 5300 5300 50 0001 C CNN +F 4 "V" H 5300 5300 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 5300 5300 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5300 5300 50 0001 C CNN "Spice_Netlist_Enabled" + 1 5300 5300 + 1 0 0 -1 +$EndComp +Text GLabel 5100 4700 0 50 Input ~ 0 +vdd +$Comp +L power:GND #PWR03 +U 1 1 5B28D086 +P 5300 5800 +F 0 "#PWR03" H 5300 5550 50 0001 C CNN +F 1 "GND" H 5305 5627 50 0000 C CNN +F 2 "" H 5300 5800 50 0001 C CNN +F 3 "" H 5300 5800 50 0001 C CNN + 1 5300 5800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 4700 5300 4700 +Wire Wire Line + 5300 4700 5300 5000 +Wire Wire Line + 5300 5600 5300 5800 +Text Notes 7500 5550 0 50 ~ 0 +.tran 1m 400m +$EndSCHEMATC diff --git a/digital ciruits/and_sub/b3v33check.log b/digital ciruits/and_sub/b3v33check.log new file mode 100644 index 0000000..6e015ea --- /dev/null +++ b/digital ciruits/and_sub/b3v33check.log @@ -0,0 +1,4 @@ +BSIM3v3.3.0 Parameter Checking. +Model = mpmos +Warning: Pd = 0 is less than W. +Warning: Ps = 0 is less than W. diff --git a/digital ciruits/and_sub/basic_gates.bck b/digital ciruits/and_sub/basic_gates.bck new file mode 100644 index 0000000..5f3ed79 --- /dev/null +++ b/digital ciruits/and_sub/basic_gates.bck @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/digital ciruits/and_sub/basic_gates.dcm b/digital ciruits/and_sub/basic_gates.dcm new file mode 100644 index 0000000..5f3ed79 --- /dev/null +++ b/digital ciruits/and_sub/basic_gates.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/digital ciruits/and_sub/basic_gates.lib b/digital ciruits/and_sub/basic_gates.lib new file mode 100644 index 0000000..a4829ad --- /dev/null +++ b/digital ciruits/and_sub/basic_gates.lib @@ -0,0 +1,56 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# UA741 +# +DEF UA741 X 0 40 Y Y 1 F N +F0 "X" 0 -250 50 H V C CNN +F1 "UA741" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 4 0 1 0 -200 200 -200 -200 300 0 -200 200 N +X + 1 -300 100 100 R 50 50 1 1 I +X - 2 -300 -100 100 R 50 50 1 1 I +X ~ 3 400 0 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# and +# +DEF and X 0 40 Y Y 1 F N +F0 "X" 0 250 50 H V C CNN +F1 "and" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +A 250 0 206 760 -760 0 1 0 N 300 200 300 -200 +P 2 0 1 0 -350 -200 300 -200 N +P 2 0 1 0 -350 200 -350 -200 N +P 2 0 1 0 -350 200 300 200 N +X A 1 -450 100 100 R 50 50 1 1 I +X B 2 -450 -100 100 R 50 50 1 1 I +X Out 3 550 0 100 L 50 50 1 1 O +X VDD 4 150 300 100 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# jkff +# +DEF jkff X 0 40 Y Y 1 F N +F0 "X" 0 -350 50 H V C CNN +F1 "jkff" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +S -350 250 350 -300 0 1 0 N +X J 1 -450 200 100 R 50 50 1 1 I +X clk 2 -450 0 100 R 50 50 1 1 I +X k 3 -450 -200 100 R 50 50 1 1 I +X vdd 4 0 350 100 D 50 50 1 1 O +X q 5 450 150 100 L 50 50 1 1 O +X nq 6 450 -200 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/and_sub/sym-lib-table b/digital ciruits/and_sub/sym-lib-table new file mode 100644 index 0000000..e843b54 --- /dev/null +++ b/digital ciruits/and_sub/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name basic_gates)(type Legacy)(uri /home/akshay/kicad_examples/and_sub/basic_gates.lib)(options "")(descr "")) +) |