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author | athulms22 | 2018-06-28 19:56:11 +0530 |
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committer | GitHub | 2018-06-28 19:56:11 +0530 |
commit | 74d7014951c8db1a0baf046648de2e5abc84d6fc (patch) | |
tree | 53fcdf704e53fdd1400a9fdb63f8bd63e1d7dedd /analog circuits/RC/RC.bak | |
parent | a45cefdde8fb6bf4739c1d5280dfea721bb4477c (diff) | |
download | eSIm-Kicad-Simulations-master.tar.gz eSIm-Kicad-Simulations-master.tar.bz2 eSIm-Kicad-Simulations-master.zip |
Diffstat (limited to 'analog circuits/RC/RC.bak')
-rw-r--r-- | analog circuits/RC/RC.bak | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/analog circuits/RC/RC.bak b/analog circuits/RC/RC.bak index 8b6bea6..2ad644c 100644 --- a/analog circuits/RC/RC.bak +++ b/analog circuits/RC/RC.bak @@ -24,7 +24,7 @@ F 2 "" H 3600 3850 50 0001 C CNN F 3 "" H 3600 3850 50 0001 C CNN
F 4 "V" H 3600 3850 50 0001 C CNN "Spice_Primitive"
F 5 "Y" H 3600 3850 50 0001 C CNN "Spice_Netlist_Enabled"
-F 6 "pwl(0m 0 0.5m 5 50m 5 50.5m 0 100m 0)" H 3600 3850 50 0001 C CNN "Spice_Model"
+F 6 "pwl(50m 5 50.5m 0 100m 0 500u 5 0m 0)" H 3600 3850 50 0001 C CNN "Spice_Model"
1 3600 3850
1 0 0 -1
$EndComp
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