summaryrefslogtreecommitdiff
path: root/webtronix_server/spice
diff options
context:
space:
mode:
authorNiel Mishra2015-09-11 15:55:11 +0530
committerNiel Mishra2015-09-11 15:55:11 +0530
commit769fcf719320e5b9c740f455630aeb44b3deb575 (patch)
treeac219a58b81d3e1cfc8e3332a006ab2f874fd21b /webtronix_server/spice
parentdbd3f0a9ea8dc6f655b4db33885ec4144db18805 (diff)
downloadeSIM-webapp-769fcf719320e5b9c740f455630aeb44b3deb575.tar.gz
eSIM-webapp-769fcf719320e5b9c740f455630aeb44b3deb575.tar.bz2
eSIM-webapp-769fcf719320e5b9c740f455630aeb44b3deb575.zip
First Commit
Diffstat (limited to 'webtronix_server/spice')
-rwxr-xr-xwebtronix_server/spice/2n7000.mod43
-rwxr-xr-xwebtronix_server/spice/555.mod54
-rwxr-xr-xwebtronix_server/spice/ad620a.mod143
-rwxr-xr-xwebtronix_server/spice/ad8221.mod141
-rwxr-xr-xwebtronix_server/spice/bat54.mod25
-rwxr-xr-xwebtronix_server/spice/digital.lib14
-rwxr-xr-xwebtronix_server/spice/dsource.mod6
-rwxr-xr-xwebtronix_server/spice/ina128.mod274
-rwxr-xr-xwebtronix_server/spice/irf150.mod62
-rwxr-xr-xwebtronix_server/spice/irf530.mod68
-rwxr-xr-xwebtronix_server/spice/irfz44n.mod68
-rwxr-xr-xwebtronix_server/spice/lm324.mod70
-rwxr-xr-xwebtronix_server/spice/lm339.mod32
-rwxr-xr-xwebtronix_server/spice/lm358.mod118
-rwxr-xr-xwebtronix_server/spice/lm741.mod111
-rwxr-xr-xwebtronix_server/spice/models.lib72
-rwxr-xr-xwebtronix_server/spice/mymodels.lib26
-rwxr-xr-xwebtronix_server/spice/mysubckt.mod131
-rwxr-xr-xwebtronix_server/spice/ne555.mod686
-rwxr-xr-xwebtronix_server/spice/tl084.mod53
-rwxr-xr-xwebtronix_server/spice/ua741.mod58
21 files changed, 2255 insertions, 0 deletions
diff --git a/webtronix_server/spice/2n7000.mod b/webtronix_server/spice/2n7000.mod
new file mode 100755
index 0000000..22c86d2
--- /dev/null
+++ b/webtronix_server/spice/2n7000.mod
@@ -0,0 +1,43 @@
+* 2N7000 model
+* External Node Designations
+* Node 1 -> Drain
+* Node 2 -> Gate
+* Node 3 -> Source
+
+.SUBCKT 2n7000 1 2 3
+M1 9 7 8 8 MM L=100u W=100u
+
+.MODEL MM NMOS LEVEL=1 IS=1e-32
++VTO=2.236 LAMBDA=0 KP=0.0932174
++CGSO=1.79115e-07 CGDO=1.0724e-11
+
+RS 8 3 1.10523
+D1 3 1 MD
+
+.MODEL MD D IS=2.71011e-10 RS=0.0140826 N=1.5 BV=60
++IBV=1e-05 EG=1.16084 XTI=3.00131 TT=0
++CJO=3.41211e-11 VJ=4.67429 M=0.899864 FC=0.1
+
+RDS 3 1 2.4e+11
+RD 9 1 0.0001
+RG 2 7 2.18034
+D2 4 5 MD1
+
+.MODEL MD1 D IS=1e-32 N=50
++CJO=7.93181e-11 VJ=0.643298 M=0.9 FC=1e-08
+
+D3 0 5 MD2
+.MODEL MD2 D IS=1e-10 N=0.400165 RS=3.00002e-06
+
+RL 5 10 1
+FI2 7 9 VFI2 -1
+VFI2 4 0 0
+EV16 10 0 9 7 1
+CAP 11 10 1.58786e-10
+FI1 7 9 VFI1 -1
+VFI1 11 6 0
+RCAP 6 10 1
+D4 0 6 MD3
+
+.MODEL MD3 D IS=1e-10 N=0.400165
+.ENDS 2n7000
diff --git a/webtronix_server/spice/555.mod b/webtronix_server/spice/555.mod
new file mode 100755
index 0000000..43da404
--- /dev/null
+++ b/webtronix_server/spice/555.mod
@@ -0,0 +1,54 @@
+.
+.SUBCKT 555 34 32 30 19 23 33 1 21
+* G TR O R F TH D V
+Q4 25 2 3 QP
+Q5 34 6 3 QP
+Q6 6 6 8 QP
+R1 9 21 4.7K
+R2 3 21 830
+R3 8 21 4.7K
+Q7 2 33 5 QN
+Q8 2 5 17 QN
+Q9 6 4 17 QN
+Q10 6 23 4 QN
+Q11 12 20 10 QP
+R4 10 21 1K
+Q12 22 11 12 QP
+Q13 14 13 12 QP
+Q14 34 32 11 QP
+Q15 14 18 13 QP
+R5 14 34 100K
+R6 22 34 100K
+R7 17 34 10K
+Q16 1 15 34 QN
+Q17 15 19 31 QP
+R8 18 23 5K
+R9 18 34 5K
+R10 21 23 5K
+Q18 27 20 21 QP
+Q19 20 20 21 QP
+R11 20 31 5K
+D1 31 24 DA
+Q20 24 25 34 QN
+Q21 25 22 34 QN
+Q22 27 24 34 QN
+R12 25 27 4.7K
+R13 21 29 6.8K
+Q23 21 29 28 QN
+Q24 29 27 16 QN
+Q25 30 26 34 QN
+Q26 21 28 30 QN
+D2 30 29 DA
+R14 16 15 100
+R15 16 26 220
+R16 16 34 4.7K
+R17 28 30 3.9K
+Q3 2 2 9 QP
+.MODEL DA D (RS=40 IS=1.0E-14 CJO=1PF)
+.MODEL QP PNP (level=1 BF=20 BR=0.02 RC=4 RB=25 IS=1.0E-14 VA=50 NE=2)
++ CJE=12.4P VJE=1.1 MJE=.5 CJC=4.02P VJC=.3 MJC=.3 TF=229P TR=159N)
+.MODEL QN NPN (level=1 IS=5.07F NF=1 BF=100 VAF=161 IKF=30M ISE=3.9P NE=2
++ BR=4 NR=1 VAR=16 IKR=45M RE=1.03 RB=4.12 RC=.412 XTB=1.5
++ CJE=12.4P VJE=1.1 MJE=.5 CJC=4.02P VJC=.3 MJC=.3 TF=229P TR=959P)
+.ENDS
+ \ No newline at end of file
diff --git a/webtronix_server/spice/ad620a.mod b/webtronix_server/spice/ad620a.mod
new file mode 100755
index 0000000..fb5d1f8
--- /dev/null
+++ b/webtronix_server/spice/ad620a.mod
@@ -0,0 +1,143 @@
+* AD620A SPICE Macro-model
+* Description: Amplifier
+* Generic Desc: 30/36V Bipolar, Inamp, prec G=1-10,000
+* Developed by: ARG/ADSC
+* Revision History: 08/10/2012 - Updated to new header style
+* 1.0 - Added V2,V3,V12,V13 and D3,D4,D15,D16 to clamp inputs to Q3,Q4 to prevent output phase reversal.
+* Copyright 1990, 2012 by Analog Devices, Inc.
+*
+* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
+* indicates your acceptance with the terms and provisions in the License Statement.
+*
+* BEGIN Notes:
+*
+* Not Modeled:
+*
+* Parameters modeled include:
+* This version of the AD620 model simulates the worst-case parameters of the 'A' grade.
+* The worst-case parameters
+* used correspond to those in the data sheet.
+*
+* END Notes
+*
+* Node assignments
+* non-inverting input
+* | inverting input
+* | | positive supply
+* | | | negative supply
+* | | | | output
+* | | | | | ref
+* | | | | | | rg1
+* | | | | | | | rg2
+* | | | | | | | |
+*.SUBCKT AD620A 1 2 99 50 46 20 7 8
+.SUBCKT AD620A 1 7 8 2 50 20 46 99
+*
+* INPUT STAGE
+*
+I1 7 50 5.002E-6
+I2 8 50 5.002E-6
+IOS 3 4 0.5E-9
+VIOS 21 3 125E-6
+CCM 3 4 2E-12
+CD1 3 0 2E-12
+CD2 4 0 2E-12
+Q1 5 4 7 QN1
+Q2 6 21 8 QN1
+D1 7 4 DX
+D2 8 21 DX
+R1 1 3 400
+R2 2 4 400
+R3 99 5 100E3
+R4 99 6 100E3
+R5 7 9 24.7E3
+R6 8 10 24.7E3
+E1 9 46 (11,5) 375E6
+E2 10 46 (11,6) 375E6
+V1 99 11 0.5
+RV1 99 11 1E3
+CC1 5 9 4E-12
+CC2 6 10 4E-12
+*
+* DIFFERENCE AMPLIFIER AND POLE AT 1MHZ
+*
+I3 18 50 5E-6
+R7 99 12 11.937E3
+R8 99 15 11.937E3
+R9 14 18 1.592E3
+R10 17 18 1.592E3
+R11 9 13 10E3
+R12 13 46 10E3
+Q3 12 13 14 QN2
+Q4 15 16 17 QN2
+R13 19 16 10E3
+R14 16 20 10E3
+C1 12 15 6.667E-12
+EOOS 19 10 POLY(1) (38,98) 1.5E-3 223.872
+*EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5
+EREF1 98 100 99 0 0.5
+EREF2 100 0 50 0 0.5
+D3 13 51 DX
+D4 16 52 DX
+V2 99 51 0.7
+V3 99 52 0.7
+D15 53 13 DX
+D16 54 16 DX
+V12 53 50 0.7
+V13 54 50 0.7
+*
+* GAIN STAGE AND DOMINANT POLE AT 0.667HZ
+*
+R16 25 98 35.810E9
+C2 25 98 6.667E-12
+G1 98 25 (12,15) 83.776E-6
+V6 99 26 1.53
+V7 27 50 1.33
+D7 25 26 DX
+D8 27 25 DX
+*
+* POLE AT 10MHZ
+*
+R17 40 98 1
+C3 40 98 15.916E-9
+G2 98 40 (25,98) 1
+*
+* COMMON MODE STAGE WITH ZERO AT 708HZ
+*
+* E3 36 98 POLY(2) (1,98) (2,98) 0 0.5 0.5
+E31 36 37 1 98 0.5
+E32 37 98 2 98 0.5
+R18 36 38 1E6
+R19 38 98 1
+C5 36 38 224.812E-12
+*
+* OUTPUT STAGE
+*
+GSY 99 50 POLY(1) (99,50) 1.1725E-3 3.125E-6
+RO1 99 45 250
+RO2 45 50 250
+L1 45 46 1E-6
+GO1 45 99 (99,40) 4E-3
+GO2 50 45 (40,50) 4E-3
+GC1 43 50 (40,45) 4E-3
+GC2 44 50 (45,40) 4E-3
+F1 45 0 V4 1
+F2 0 45 V5 1
+V4 41 45 1.65
+V5 45 42 1.65
+D9 50 43 DY
+D10 50 44 DY
+D11 99 43 DX
+D12 99 44 DX
+D13 40 41 DX
+D14 42 40 DX
+*
+* MODELS USED
+*
+.MODEL DX D(IS=1E-12)
+.MODEL DY D(IS=1E-12 BV=50)
+.MODEL QN1 NPN(BF=2.5E3 KF=0.7E-15 AF=1)
+.MODEL QN2 NPN(BF=250 KF=0.5E-14 AF=1)
+.ENDS AD620A
+
+
diff --git a/webtronix_server/spice/ad8221.mod b/webtronix_server/spice/ad8221.mod
new file mode 100755
index 0000000..54fb5ef
--- /dev/null
+++ b/webtronix_server/spice/ad8221.mod
@@ -0,0 +1,141 @@
+* AD8221 SPICE Macro-model
+* Description: Amplifier
+* Generic Desc: 30/36V Bipolar, IN AMP, Hi CMRR ,Single
+* Developed by: PRB IAP ADI
+* Revision History: 08/10/2012 - Updated to new header style
+* 1.0 (10/2010) - Changed Negative Zero stage to remove the
+* negative capacitor value.
+* Copyright 2012 by Analog Devices.
+*
+* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
+* indicates your acceptance with the terms and provisions in the License Statement.
+*
+* BEGIN Notes:
+*
+* Not Modeled:
+* Temperature effects
+* PSRR
+* Parameters modeled include:
+*
+* END Notes
+*
+* Node assignments
+* inverting input
+* | RG
+* | | RG
+* | | | non_inverting input
+* | | | | negative supply
+* | | | | | ref
+* | | | | | | output
+* | | | | | | | positive supply
+* | | | | | | | |
+.SUBCKT AD8221 IN- RG- RG+ IN+ -Vs REF VOUT +Vs
+** INPUT STAGER1 sub_out sub_neg 10E3
+R1 sub_out sub_neg 10E3
+R2 sub_neg Inverting_Out 10E3
+R3 sub_pos noninverting_out 10001
+R4 REF sub_pos 10k
+R5 RG- N003 24700
+R6 RG+ N010 24724
+D3 N003 P001 D
+D4 P002 N003 D
+V3 P002 VNEGx 0.94
+V4 VPOSx P001 .71
+D5 N010 P003 D
+D6 P004 N010 D
+V5 P004 VNEGx 0.94
+V6 VPOSx P003 .71
+D7 N005 P005 D
+D8 P006 N005 D
+V7 P006 VNEGx 2.0
+V8 VPOSx P005 1.7
+D9 N016 P007 D
+D10 P008 N016 D
+V9 P008 VNEGx 2.0
+V10 VPOSx P007 1.7
+D11 N009 P009 D
+D12 P010 N009 D
+V11 P010 N017 1.7
+V12 N008 P009 1.7
+D13 REF P011 D
+D14 P012 REF D
+V13 P012 VNEGx .3
+V14 VPOSx P011 .3
+D15 sub_pos P013 D
+D16 P014 sub_pos D
+V15 P014 VNEGx 0.9
+V16 VPOSx P013 0.9
+E4 Inverting_Out 0 N003 0 1
+E5 noninverting_out 0 N010 0 1
+V1 VBIAS +Vs 20
+I1 VBIAS Pos_Fdbk 20E-6
+I2 VBIAS Inv_Fdbk 20E-6
+C1 N003 Inv_Fdbk 9.235e-12
+C2 N010 Pos_Fdbk 9.2e-12
+E8 N002 0 N005 0 1
+E9 N013 0 N016 0 1
+VOSI_Neg N004 IN- 25E-6
+VOSI_Pos IN+ N014 24E-6
+VOSO VOUT N009 300E-6
+C3 RG- 0 .200e-12
+C4 RG+ 0 .135e-12
+I23 IN- 0 1.4E-9
+I24 IN+ 0 0.8E-9
+G1 0 IN+ N018 N019 .0025e-9
+R13 IN+ N018 10e9
+R14 N018 IN- 10e9
+R15 +Vs N019 10e9
+R16 N019 -Vs 10e9
+G2 0 IN- N018 N019 .0025e-9
+E10 VPOSx 0 +Vs 0 1
+I3 +Vs -Vs 900E-6
+G3 +Vs -Vs +Vs -Vs 1e-6
+E11 VNEGx 0 -Vs 0 1
+
+H3 N006 N004 V24 4.5
+V24 N001 0 0
+R19 N001 0 .0166
+H4 VX sub_out V25 64
+V25 N007 0 0
+R20 N007 0 .0166
+H5 N015 N014 V26 4.5
+V26 N011 0 0
+R21 N011 0 .0166
+G4 0 N005 N006 N005 1
+G5 0 N016 N015 N016 1
+G6 0 N003 VBIAS Inv_Fdbk 1
+G7 0 N010 VBIAS Pos_Fdbk 1
+G8 0 sub_out sub_pos sub_neg 1
+R10 N005 0 10e9
+R7 N003 0 10E9
+R11 N016 0 10E9
+R8 N010 0 10E9
+R9 sub_out 0 10E9
+Q1 Pos_Fdbk N013 RG+ 0 NPN
+Q2 Inv_Fdbk N002 RG- 0 NPN
+G9 0 N012 VY N009 1
+G10 0 N009 N012 0 .002
+R12 N012 0 1e10
+R17 N009 0 500
+C5 N012 0 1.4e-7
+C6 N009 0 700e-12
+C8 VY 0 1e-9
+*G11 0 VY VALUE = { LIMIT( 1*V(VX,VY), .002, -.002) }
+g11 0 vy vx vy fit ( -18, -.002 18, .002 ) order=1 above=.002 below=-.002
+R22 VY 0 1e9
+R18 VBIAS Inv_Fdbk 1e9
+R23 Pos_Fdbk VBIAS 1e9
+D1 sub_out P015 D
+V2 VPOSx P015 1.7
+D2 P016 sub_out D
+V17 P016 VNEGx 1.7
+
+H1 VPOSx N008 POLY(1) VOSO 0 0 8000
+H2 N017 VNEGx POLY(1) VOSO 0 0 8000
+
+* MODELS USED
+*
+.model D D
+.model NPN NPN
+.ENDS AD8221
+
diff --git a/webtronix_server/spice/bat54.mod b/webtronix_server/spice/bat54.mod
new file mode 100755
index 0000000..f858656
--- /dev/null
+++ b/webtronix_server/spice/bat54.mod
@@ -0,0 +1,25 @@
+*
+.SUBCKT BAT54 1 3
+* The Resistor R1 does not reflect
+* a physical device. Instead it
+* improves modeling in the reverse
+* mode of operation.
+*
+R1 1 3 3.6E+07
+D1 1 3 BAT54
+*
+.MODEL BAT54 D(
++ IS = 2.117E-07
++ N = 1.016
++ BV = 36
++ IBV = 1.196E-06
++ RS = 2.637
++ CJO = 1.114E-11
++ VJ = 0.2013
++ M = 0.3868
++ FC = 0
++ TT = 0
++ EG = 0.69
++ XTI = 2)
+*
+.ENDS BAT54 \ No newline at end of file
diff --git a/webtronix_server/spice/digital.lib b/webtronix_server/spice/digital.lib
new file mode 100755
index 0000000..90d15c5
--- /dev/null
+++ b/webtronix_server/spice/digital.lib
@@ -0,0 +1,14 @@
+.model and1 and(rise = 0.5e-9 fall = 0.3e-9)
+
+.model nand1 nand(rise = 0.5e-9 fall = 0.3e-9)
+
+.model or1 or(rise = 0.5e-9 fall = 0.3e-9)
+
+.model nor1 nor(rise = 0.5e-9 fall = 0.3e-9)
+
+.model xor1 xor(rise = 0.5e-9 fall= 0.3e-9)
+
+.model inv1 inv(rise = 0.5e-9 fall = 0.3e-9)
+
+
+
diff --git a/webtronix_server/spice/dsource.mod b/webtronix_server/spice/dsource.mod
new file mode 100755
index 0000000..3e90949
--- /dev/null
+++ b/webtronix_server/spice/dsource.mod
@@ -0,0 +1,6 @@
+.SUBCKT clk 1
+
+vclk 0 1 pulse(0 -5 0 0 0 1m 2m)
+
+.ENDS
+
diff --git a/webtronix_server/spice/ina128.mod b/webtronix_server/spice/ina128.mod
new file mode 100755
index 0000000..dad3935
--- /dev/null
+++ b/webtronix_server/spice/ina128.mod
@@ -0,0 +1,274 @@
+
+
+* INA128
+*****************************************************************************
+* (C) Copyright 2011 Texas Instruments Incorporated. All rights reserved.
+*****************************************************************************
+** This model is designed as an aid for customers of Texas Instruments.
+** TI and its licensors and suppliers make no warranties, either expressed
+** or implied, with respect to this model, including the warranties of
+** merchantability or fitness for a particular purpose. The model is
+** provided solely on an "as is" basis. The entire risk as to its quality
+** and performance is with the customer.
+*****************************************************************************
+*
+* This model is subject to change without notice. Texas Instruments
+* Incorporated is not responsible for updating this model.
+*
+*****************************************************************************
+*
+** Released by: Analog eLab Design Center, Texas Instruments Inc.
+* Part: INA128
+* Date: 08JUL2011
+* Model Type: ALL IN ONE
+* Simulator: PSPICE
+* Simulator Version: 16.0.0.p001
+* EVM Order Number: N/A
+* EVM Users Guide: N/A
+* Datasheet: SBOS051B - OCTOBER 1995 - REVISED FEBRUARY 2005
+*
+* Model Version: 1.0
+*
+*****************************************************************************
+*
+* Updates:
+*
+* Version 1.0 :
+* Release to Web
+*
+*****************************************************************************
+* COMMENTS
+* CONNECTIONS: +
+* | -
+* | | V+
+* | | | V-
+* | | | | Out
+* | | | | | REF
+* | | | | | | RG1
+* | | | | | | | RG2
+* | | | | | | | |
+* PIN CONFIG FOR INA128 1 2 3 4 5 8 9 10
+*****************************************************************************
+
+.SUBCKT INA128 1 2 3 4 5 8 9 10
+
+X1 15 17 3 4 11 A1_128E
+X2 15 16 3 4 12 A2_128E
+X3 14 13 3 4 5 A3_128E
+*
+R1 11 13 40.0000K
+R2 13 5 39.996K
+R3 12 14 40.0000K
+R4 14 8 40.0000K
+CIN 13 14 4.0000PF
+*
+R1FB 9 11 25.000K
+CC1 17 11 5.0000PF
+R2FB 10 12 25.000K
+CC2 16 12 5.0000PF
+CG1 9 0 10.0000PF
+CG2 10 0 8.0000PF
+*
+RCE 17 9 20G
+*
+I1 3 16 DC 20.00E-6
+I2 3 17 DC 20.00E-6
+IB1CAN 3 42 DC 40.00E-9
+IB2CAN 3 46 DC 40.00E-9
+IBAL 0 4 DC 6.5E-6
+*
+D1 15 17 DX
+D2 15 16 DX
+*
+Q1 16 42 10 QX
+Q2 17 46 9 QX
+*
+V1 3 15 DC 1.700
+
+* INPUT PROTECTION
+ RIN1 1 41 1K
+ I11 41 42 .7MA
+ S11 41 42 1 41 SP
+ DI1 43 41 DX
+ I12 4 43 DC .8MA
+ S12 4 43 1 41 SM
+
+ RIN2 2 45 1K
+ I21 45 46 .7MA
+ S21 45 46 2 45 SP
+ DI2 47 45 DX
+ I22 4 47 DC .8MA
+ S22 4 47 2 45 SM
+
+* Anti-inversion clamps *
+ VSET1 3 40 DC 2.0
+ QSET1 4 40 42 QY
+ VSET2 3 44 DC 2.0
+ QSET2 4 44 46 QY
+
+.model sp vswitch(ron=10 roff=100E3 von=.7 voff=1)
+.model sm vswitch(ron=10 roff=100E3 von=-.7 voff=-1)
+.MODEL DX D(IS=1.0E-24)
+.MODEL QX NPN(IS=800.0E-18 BF=500)
+.MODEL QY PNP(IS=800.0E-18 BF=500)
+.ENDS INA128
+*
+* connections: non-inverting input
+* | inverting input
+* | | positive power supply
+* | | | negative power supply
+* | | | | output
+* | | | | |
+.subckt A1_128E 1 2 3 4 5
+*
+ c1 11 12 2.887E-12
+ c2 6 7 10.00E-12
+ css 10 99 1.000E-30
+ dc 5 53 dx
+ de 54 5 dx
+ dlp 90 91 dx
+ dln 92 90 dx
+ dp 4 3 dx
+* egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5
+ egnd 99 0 3 0 .5
+ egnd 99 0 4 0 .5
+* fb 7 99 poly(5) vb vc ve vlp vln 0 79.58E6 -80E6 80E6 80E6 -80E6
+ fb 7 99 vb 79.58E6
+ fb 7 99 vc -80E6
+ fb 7 99 ve 80E6
+ fb 7 vlp 80E6
+ fb 7 vln -80E6
+ ga 6 0 11 12 1.257E-3
+ gcm 0 6 10 99 125.7E-12
+ iss 3 10 dc 50.00E-6
+ hlim 90 0 vlim 1K
+ j1 11 2 10 jx
+ j2 12 1 10 jx
+ r2 6 9 100.0E3
+ rd1 4 11 795.8
+ rd2 4 12 795.8
+ ro1 8 5 10
+ ro2 7 99 10
+ rss 10 99 4.000E6
+ vb 9 0 dc 0
+ vc 3 53 dc 1.5
+ ve 54 4 dc .9
+ vlim 7 8 dc 0
+ vlp 91 0 dc 14
+ vln 0 92 dc 14
+
+* OUTPUT SUPPLY MIRROR
+ FQ3 0 20 POLY(1) VLIM 0 1
+ DQ1 20 21 DX
+ DQ2 22 20 DX
+ VQ1 21 0 0
+ VQ2 22 0 0
+ FQ1 3 0 POLY(1) VQ1 120u 1
+ FQ2 0 4 POLY(1) VQ2 120u -1
+ RP 3 4 3.00E6
+
+.model dx D(Is=800.0E-18)
+.model jx PJF(Is=15.00E-12 Beta=31.58E-3 Vto=-1)
+.ends
+
+* connections: non-inverting input
+* | inverting input
+* | | positive power supply
+* | | | negative power supply
+* | | | | output
+* | | | | |
+.subckt A2_128E 1 2 3 4 5
+*
+ c1 11 12 2.887E-12
+ c2 6 7 10.00E-12
+ css 10 99 1.000E-30
+ dc 5 53 dx
+ de 54 5 dx
+ dlp 90 91 dx
+ dln 92 90 dx
+ dp 4 3 dx
+ egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5
+ fb 7 99 poly(5) vb vc ve vlp vln 0 79.58E6 -80E6 80E6 80E6 -80E6
+ ga 6 0 11 12 1.257E-3
+ gcm 0 6 10 99 125.7E-12
+ iss 3 10 dc 50.00E-6
+ hlim 90 0 vlim 1K
+ j1 11 2 10 jx
+ j2 12 1 10 jx
+ r2 6 9 100.0E3
+ rd1 4 11 795.8
+ rd2 4 12 795.8
+ ro1 8 5 10
+ ro2 7 99 10
+ rss 10 99 4.000E6
+ vb 9 0 dc 0
+ vc 3 53 dc 1.5
+ ve 54 4 dc .9
+ vlim 7 8 dc 0
+ vlp 91 0 dc 14
+ vln 0 92 dc 14
+
+* OUTPUT SUPPLY MIRROR
+ FQ3 0 20 POLY(1) VLIM 0 1
+ DQ1 20 21 DX
+ DQ2 22 20 DX
+ VQ1 21 0 0
+ VQ2 22 0 0
+ FQ1 3 0 POLY(1) VQ1 120u 1
+ FQ2 0 4 POLY(1) VQ2 120u -1
+ RP 3 4 3.00E6
+
+.model dx D(Is=800.0E-18)
+.model jx PJF(Is=15.00E-12 Beta=31.58E-3 Vto=-1)
+.ends
+
+* connections: non-inverting input
+* | inverting input
+* | | positive power supply
+* | | | negative power supply
+* | | | | output
+* | | | | |
+.subckt A3_128E 1 2 3 4 5
+*
+ c1 11 12 2.730E-12
+ c2 6 7 15.00E-12
+ dc 5 53 dx
+ de 54 5 dx
+ dlp 90 91 dx
+ dln 92 90 dx
+ dp 4 3 dx
+ egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5
+ fb 7 99 poly(5) vb vc ve vlp vln 0 163.2E6 -160E6 160E6 160E6 -160E6
+ ga 6 0 11 12 122.5E-6
+ gcm 0 6 10 99 12.25E-12
+ iee 10 4 dc 63.95E-6
+ hlim 90 0 vlim 1K
+ q1 11 2 13 qx
+ q2 12 1 14 qx
+ r2 6 9 100.0E3
+ rc1 3 11 8.162E3
+ rc2 3 12 8.162E3
+ re1 13 10 7.327E3
+ re2 14 10 7.327E3
+ ree 10 99 3.127E6
+ ro1 8 5 300
+ ro2 7 99 300
+ vb 9 0 dc 0
+ vc 3 53 dc 1.500
+ ve 54 4 dc 1.400
+ vlim 7 8 dc 0
+ vlp 91 0 dc 5
+ vln 0 92 dc 14
+
+*OUTPUT SUPPLY MIRROR
+ FQ3 0 20 POLY(1) VLIM 0 1
+ DQ1 20 21 DX
+ DQ2 22 20 DX
+ VQ1 21 0 0
+ VQ2 22 0 0
+ FQ1 3 0 POLY(1) VQ1 206.7E-6 1
+ FQ2 0 4 POLY(1) VQ2 206.7E-6 -1
+ RQ 3 4 1.87e6
+.model dx D(Is=800.0E-18)
+.model qx NPN(Is=800.0E-18 Bf=318.8)
+.ends
diff --git a/webtronix_server/spice/irf150.mod b/webtronix_server/spice/irf150.mod
new file mode 100755
index 0000000..cd21fb0
--- /dev/null
+++ b/webtronix_server/spice/irf150.mod
@@ -0,0 +1,62 @@
+
+.SUBCKT irf150 1 2 3 100
+**************************************
+* Model Generated by MODPEX *
+*Copyright(c) Symmetry Design Systems*
+* All Rights Reserved *
+* UNPUBLISHED LICENSED SOFTWARE *
+* Contains Proprietary Information *
+* Which is The Property of *
+* SYMMETRY OR ITS LICENSORS *
+*Commercial Use or Resale Restricted *
+* by Symmetry License Agreement *
+**************************************
+* Model generated on Dec 17, 96
+* MODEL FORMAT: SPICE3
+* Symmetry POWER MOS Model (Version 1.0)
+* External Node Designations
+* Node 1 -> Drain
+* Node 2 -> Gate
+* Node 3 -> Source
+M1 9 7 8 8 MM L=100u W=100u
+* Default values used in MM:
+* The voltage-dependent capacitances are
+* not included. Other default values are:
+* RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0
+.MODEL MM NMOS LEVEL=1 IS=1e-32
++VTO=4.07861 LAMBDA=0.000761669 KP=19.0218
++CGSO=3.57784e-05 CGDO=4.96221e-07
+RS 8 3 0.0216597
+D1 3 1 MD
+.MODEL MD D IS=2.01865e-09 RS=0.11592 N=1.5 BV=100
++IBV=0.001 EG=1 XTI=1 TT=1e-07
++CJO=3.28974e-09 VJ=4.39387 M=0.659734 FC=0.1
+RDS 3 1 3.2e+06
+RD 9 1 0.00224103
+RG 2 7 12.1
+D2 4 5 MD1
+* Default values used in MD1:
+* RS=0 EG=1.11 XTI=3.0 TT=0
+* BV=infinite IBV=1mA
+.MODEL MD1 D IS=1e-32 N=50
++CJO=3.78329e-09 VJ=0.607074 M=0.893797 FC=1e-08
+D3 0 5 MD2
+* Default values used in MD2:
+* EG=1.11 XTI=3.0 TT=0 CJO=0
+* BV=infinite IBV=1mA
+.MODEL MD2 D IS=1e-10 N=0.402271 RS=3.00001e-06
+RL 5 10 1
+FI2 7 9 VFI2 -1
+VFI2 4 0 0
+EV16 10 0 9 7 1
+CAP 11 10 3.78329e-09
+FI1 7 9 VFI1 -1
+VFI1 11 6 0
+RCAP 6 10 1
+D4 0 6 MD3
+* Default values used in MD3:
+* EG=1.11 XTI=3.0 TT=0 CJO=0
+* RS=0 BV=infinite IBV=1mA
+.MODEL MD3 D IS=1e-10 N=0.402271
+.ENDS irf150
+
diff --git a/webtronix_server/spice/irf530.mod b/webtronix_server/spice/irf530.mod
new file mode 100755
index 0000000..f003c2f
--- /dev/null
+++ b/webtronix_server/spice/irf530.mod
@@ -0,0 +1,68 @@
+*Feb 16, 2010
+*Doc. ID: 90181, Rev. A
+*File Name: part irf530_PS.txt and part irf530_PS.spi
+*This document is intended as a SPICE modeling guideline and does not
+*constitute a commercial product data sheet. Designers should refer to the
+*appropriate data sheet of the same number for guaranteed specification
+*limits.
+.SUBCKT irf530 1 2 3 100
+**************************************
+* Model Generated by MODPEX *
+*Copyright(c) Symmetry Design Systems*
+* All Rights Reserved *
+* UNPUBLISHED LICENSED SOFTWARE *
+* Contains Proprietary Information *
+* Which is The Property of *
+* SYMMETRY OR ITS LICENSORS *
+*Commercial Use or Resale Restricted *
+* by Symmetry License Agreement *
+**************************************
+* Model generated on Apr 24, 96
+* Model format: SPICE3
+* Symmetry POWER MOS Model (Version 1.0)
+* External Node Designations
+* Node 1 -> Drain
+* Node 2 -> Gate
+* Node 3 -> Source
+M1 9 7 8 8 MM L=100u W=100u
+* Default values used in MM:
+* The voltage-dependent capacitances are
+* not included. Other default values are:
+* RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0
+.MODEL MM NMOS LEVEL=1 IS=1e-32
++VTO=3.87932 LAMBDA=0.00393789 KP=7.05019
++CGSO=6.11314e-06 CGDO=1e-11
+RS 8 3 0.073836
+D1 3 1 MD
+.MODEL MD D IS=9.70956e-10 RS=0.0137423 N=1.31938 BV=300
++IBV=0.00025 EG=1 XTI=4 TT=1e-07
++CJO=1.03141e-09 VJ=1.46661 M=0.501224 FC=0.5
+RDS 3 1 4e+06
+RD 9 1 0.0001
+RG 2 7 9.77071
+D2 4 5 MD1
+* Default values used in MD1:
+* RS=0 EG=1.11 XTI=3.0 TT=0
+* BV=infinite IBV=1mA
+.MODEL MD1 D IS=1e-32 N=50
++CJO=7.50724e-10 VJ=0.801667 M=0.67327 FC=1e-08
+D3 0 5 MD2
+* Default values used in MD2:
+* EG=1.11 XTI=3.0 TT=0 CJO=0
+* BV=infinite IBV=1mA
+.MODEL MD2 D IS=1e-10 N=0.401518 RS=3e-06
+RL 5 10 1
+FI2 7 9 VFI2 -1
+VFI2 4 0 0
+EV16 10 0 9 7 1
+CAP 11 10 7.50724e-10
+FI1 7 9 VFI1 -1
+VFI1 11 6 0
+RCAP 6 10 1
+D4 0 6 MD3
+* Default values used in MD3:
+* EG=1.11 XTI=3.0 TT=0 CJO=0
+* RS=0 BV=infinite IBV=1mA
+.MODEL MD3 D IS=1e-10 N=0.401518
+.ENDS
+
diff --git a/webtronix_server/spice/irfz44n.mod b/webtronix_server/spice/irfz44n.mod
new file mode 100755
index 0000000..d2be9d0
--- /dev/null
+++ b/webtronix_server/spice/irfz44n.mod
@@ -0,0 +1,68 @@
+*Aug 17, 2010
+*Doc. ID: 90561, Rev. A
+*File Name: irfz44n_PS.txt and irfz44n_PS.spi
+*This document is intended as a SPICE modeling guideline and does not
+*constitute a commercial product datasheet. Designers should refer to the
+*appropriate data sheet of the same number for guaranteed specification
+*limits.
+.SUBCKT irfz44n 1 2 3
+**************************************
+* Model Generated by MODPEX *
+*Copyright(c) Symmetry Design Systems*
+* All Rights Reserved *
+* UNPUBLISHED LICENSED SOFTWARE *
+* Contains Proprietary Information *
+* Which is The Property of *
+* SYMMETRY OR ITS LICENSORS *
+*Commercial Use or Resale Restricted *
+* by Symmetry License Agreement *
+**************************************
+* Model generated on Apr 24, 96
+* Model format: SPICE3
+* Symmetry POWER MOS Model (Version 1.0)
+* External Node Designations
+* Node 1 -> Drain
+* Node 2 -> Gate
+* Node 3 -> Source
+M1 9 7 8 8 MM L=100u W=100u
+* Default values used in MM:
+* The voltage-dependent capacitances are
+* not included. Other default values are:
+* RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0
+.MODEL MM NMOS LEVEL=1 IS=1e-32
++VTO=3.56214 LAMBDA=0 KP=39.3974
++CGSO=1.25255e-05 CGDO=2.2826e-07
+RS 8 3 0.0133305
+D1 3 1 MD
+.MODEL MD D IS=9.64635e-13 RS=0.00967689 N=1.01377 BV=55
++IBV=0.00025 EG=1.08658 XTI=2.9994 TT=1e-07
++CJO=1.39353e-09 VJ=0.5 M=0.42532 FC=0.5
+RDS 3 1 2.2e+06
+RD 9 1 0.0001
+RG 2 7 2.20235
+D2 4 5 MD1
+* Default values used in MD1:
+* RS=0 EG=1.11 XTI=3.0 TT=0
+* BV=infinite IBV=1mA
+.MODEL MD1 D IS=1e-32 N=50
++CJO=1.52875e-09 VJ=0.5 M=0.584414 FC=1e-08
+D3 0 5 MD2
+* Default values used in MD2:
+* EG=1.11 XTI=3.0 TT=0 CJO=0
+* BV=infinite IBV=1mA
+.MODEL MD2 D IS=1e-10 N=0.408752 RS=3e-06
+RL 5 10 1
+FI2 7 9 VFI2 -1
+VFI2 4 0 0
+EV16 10 0 9 7 1
+CAP 11 10 2.06741e-09
+FI1 7 9 VFI1 -1
+VFI1 11 6 0
+RCAP 6 10 1
+D4 0 6 MD3
+* Default values used in MD3:
+* EG=1.11 XTI=3.0 TT=0 CJO=0
+* RS=0 BV=infinite IBV=1mA
+.MODEL MD3 D IS=1e-10 N=0.408752
+.ENDS
+
diff --git a/webtronix_server/spice/lm324.mod b/webtronix_server/spice/lm324.mod
new file mode 100755
index 0000000..02782bc
--- /dev/null
+++ b/webtronix_server/spice/lm324.mod
@@ -0,0 +1,70 @@
+* WARNING : please consider following remarks before usage
+*
+* 1) All models are a tradeoff between accuracy and complexity (ie. simulation
+* time).
+* 2) Macromodels are not a substitute to breadboarding, they rather confirm the
+* validity of a design approach and help to select surrounding component values.
+*
+* 3) A macromodel emulates the NOMINAL performance of a TYPICAL device within
+* SPECIFIED OPERATING CONDITIONS (ie. temperature, supply voltage, etc.).
+* Thus the macromodel is often not as exhaustive as the datasheet, its goal
+* is to illustrate the main parameters of the product.
+*
+* 4) Data issued from macromodels used outside of its specified conditions
+* (Vcc, Temperature, etc) or even worse: outside of the device operating
+* conditions (Vcc, Vicm, etc) are not reliable in any way.
+*
+*
+** Standard Linear Ics Macromodels, 1993.
+** CONNECTIONS :
+* 1 INVERTING INPUT
+* 2 NON-INVERTING INPUT
+* 3 OUTPUT
+* 4 POSITIVE POWER SUPPLY
+* 5 NEGATIVE POWER SUPPLY
+.SUBCKT LM324 2 1 4 5 3
+***************************
+.MODEL MDTH D IS=1E-8 KF=3.104131E-15 CJO=10F
+* INPUT STAGE
+CIP 2 5 1.000000E-12
+CIN 1 5 1.000000E-12
+EIP 10 5 2 5 1
+EIN 16 5 1 5 1
+RIP 10 11 2.600000E+01
+RIN 15 16 2.600000E+01
+RIS 11 15 2.003862E+02
+DIP 11 12 MDTH 400E-12
+DIN 15 14 MDTH 400E-12
+VOFP 12 13 DC 0
+VOFN 13 14 DC 0
+IPOL 13 5 1.000000E-05
+CPS 11 15 3.783376E-09
+DINN 17 13 MDTH 400E-12
+VIN 17 5 0.000000e+00
+DINR 15 18 MDTH 400E-12
+VIP 4 18 2.000000E+00
+FCP 4 5 VOFP 3.400000E+01
+FCN 5 4 VOFN 3.400000E+01
+FIBP 2 5 VOFN 2.000000E-03
+FIBN 5 1 VOFP 2.000000E-03
+* AMPLIFYING STAGE
+FIP 5 19 VOFP 3.600000E+02
+FIN 5 19 VOFN 3.600000E+02
+RG1 19 5 3.652997E+06
+RG2 19 4 3.652997E+06
+CC 19 5 6.000000E-09
+DOPM 19 22 MDTH 400E-12
+DONM 21 19 MDTH 400E-12
+HOPM 22 28 VOUT 7.500000E+03
+VIPM 28 4 1.500000E+02
+HONM 21 27 VOUT 7.500000E+03
+VINM 5 27 1.500000E+02
+EOUT 26 23 19 5 1
+VOUT 23 5 0
+ROUT 26 3 20
+COUT 3 5 1.000000E-12
+DOP 19 25 MDTH 400E-12
+VOP 4 25 2.242230E+00
+DON 24 19 MDTH 400E-12
+VON 24 5 7.922301E-01
+.ENDS
diff --git a/webtronix_server/spice/lm339.mod b/webtronix_server/spice/lm339.mod
new file mode 100755
index 0000000..0cc2417
--- /dev/null
+++ b/webtronix_server/spice/lm339.mod
@@ -0,0 +1,32 @@
+* LM339 VOLTAGE COMPARATOR "MACROMODEL" SUBCIRCUIT
+* CREATED USING PARTS VERSION 4.03 ON 03/07/90 AT 14:17
+* REV (N/A)
+* CONNECTIONS: NON-INVERTING INPUT
+* | INVERTING INPUT
+* | | POSITIVE POWER SUPPLY
+* | | | NEGATIVE POWER SUPPLY
+* | | | | OPEN COLLECTOR OUTPUT
+* | | | | |
+.SUBCKT LM339 1 2 3 4 5
+*
+ F1 9 3 V1 1
+ IEE 3 7 DC 100.0E-6
+ VI1 21 1 DC .75
+ VI2 22 2 DC .75
+ Q1 9 21 7 QIN
+ Q2 8 22 7 QIN
+ Q3 9 8 4 QMO
+ Q4 8 8 4 QMI
+.MODEL QIN PNP(IS=800.0E-18 BF=2.000E3)
+.MODEL QMI NPN(IS=800.0E-18 BF=1002)
+.MODEL QMO NPN(IS=800.0E-18 BF=1000 CJC=1E-15 TR=807.4E-9)
+ E1 10 4 9 4 1
+ V1 10 11 DC 0
+ Q5 5 11 4 QOC
+.MODEL QOC NPN(IS=800.0E-18 BF=20.29E3 CJC=1E-15 TF=942.6E-12 TR=543.8E-9)
+ DP 4 3 DX
+ RP 3 4 46.3E3
+.MODEL DX D(IS=800.0E-18)
+*
+.ENDS
+
diff --git a/webtronix_server/spice/lm358.mod b/webtronix_server/spice/lm358.mod
new file mode 100755
index 0000000..ada71b7
--- /dev/null
+++ b/webtronix_server/spice/lm358.mod
@@ -0,0 +1,118 @@
+*//////////////////////////////////////////////////////////////////////
+* (C) National Semiconductor, Inc.
+* Models developed and under copyright by:
+* National Semiconductor, Inc.
+
+*/////////////////////////////////////////////////////////////////////
+* Legal Notice: This material is intended for free software support.
+* The file may be copied, and distributed; however, reselling the
+* material is illegal
+
+*////////////////////////////////////////////////////////////////////
+* For ordering or technical information on these models, contact:
+* National Semiconductor's Customer Response Center
+* 7:00 A.M.--7:00 P.M. U.S. Central Time
+* (800) 272-9959
+* For Applications support, contact the Internet address:
+* amps-apps@galaxy.nsc.com
+
+*//////////////////////////////////////////////////////////
+*LM358 DUAL OPERATIONAL AMPLIFIER MACRO-MODEL
+*//////////////////////////////////////////////////////////
+*
+* connections: non-inverting input
+* | inverting input
+* | | positive power supply
+* | | | negative power supply
+* | | | | output
+* | | | | |
+* | | | | |
+.SUBCKT LM358 1 2 99 50 28
+*
+*Features:
+*Eliminates need for dual supplies
+*Large DC voltage gain = 100dB
+*High bandwidth = 1MHz
+*Low input offset voltage = 2mV
+*Wide supply range = +-1.5V to +-16V
+*
+*NOTE: Model is for single device only and simulated
+* supply current is 1/2 of total device current.
+* Output crossover distortion with dual supplies
+* is not modeled.
+*
+****************INPUT STAGE**************
+*
+IOS 2 1 5N
+*^Input offset current
+R1 1 3 500K
+R2 3 2 500K
+I1 99 4 100U
+R3 5 50 517
+R4 6 50 517
+Q1 5 2 4 QX
+Q2 6 7 4 QX
+*Fp2=1.2 MHz
+C4 5 6 128.27P
+*
+***********COMMON MODE EFFECT***********
+*
+I2 99 50 75U
+*^Quiescent supply current
+EOS 7 1 POLY(1) 16 49 2E-3 1
+*Input offset voltage.^
+R8 99 49 60K
+R9 49 50 60K
+*
+*********OUTPUT VOLTAGE LIMITING********
+V2 99 8 1.63
+D1 9 8 DX
+D2 10 9 DX
+V3 10 50 .635
+*
+**************SECOND STAGE**************
+*
+EH 99 98 99 49 1
+G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459
+*Fp1=7.86 Hz
+R5 98 9 101.2433MEG
+C3 98 9 200P
+*
+***************POLE STAGE***************
+*
+*Fp=2 MHz
+G3 98 15 9 49 1E-6
+R12 98 15 1MEG
+C5 98 15 7.9577E-14
+*
+*********COMMON-MODE ZERO STAGE*********
+*
+*Fpcm=10 KHz
+G4 98 16 3 49 5.6234E-8
+L2 98 17 15.9M
+R13 17 16 1K
+*
+**************OUTPUT STAGE**************
+*
+F6 50 99 POLY(1) V6 300U 1
+E1 99 23 99 15 1
+R16 24 23 17.5
+D5 26 24 DX
+V6 26 22 .63V
+R17 23 25 17.5
+D6 25 27 DX
+V7 22 27 .63V
+V5 22 21 0.27V
+D4 21 15 DX
+V4 20 22 0.27V
+D3 15 20 DX
+L3 22 28 500P
+RL3 22 28 100K
+*
+***************MODELS USED**************
+*
+.MODEL DX D(IS=1E-15)
+.MODEL QX PNP(BF=1.111E3)
+*
+.ENDS
+*$
diff --git a/webtronix_server/spice/lm741.mod b/webtronix_server/spice/lm741.mod
new file mode 100755
index 0000000..f92b0c2
--- /dev/null
+++ b/webtronix_server/spice/lm741.mod
@@ -0,0 +1,111 @@
+*//////////////////////////////////////////////////////////////////////
+* (C) National Semiconductor, Inc.
+* Models developed and under copyright by:
+* National Semiconductor, Inc.
+
+*/////////////////////////////////////////////////////////////////////
+* Legal Notice: This material is intended for free software support.
+* The file may be copied, and distributed; however, reselling the
+* material is illegal
+
+*////////////////////////////////////////////////////////////////////
+* For ordering or technical information on these models, contact:
+* National Semiconductor's Customer Response Center
+* 7:00 A.M.--7:00 P.M. U.S. Central Time
+* (800) 272-9959
+* For Applications support, contact the Internet address:
+* amps-apps@galaxy.nsc.com
+
+*//////////////////////////////////////////////////////////
+*LM741 OPERATIONAL AMPLIFIER MACRO-MODEL
+*//////////////////////////////////////////////////////////
+*
+* connections: non-inverting input
+* | inverting input
+* | | positive power supply
+* | | | negative power supply
+* | | | | output
+* | | | | |
+* | | | | |
+.SUBCKT LM741/NS 1 2 99 50 28
+*
+*Features:
+*Improved performance over industry standards
+*Plug-in replacement for LM709,LM201,MC1439,748
+*Input and output overload protection
+*
+****************INPUT STAGE**************
+*
+IOS 2 1 20N
+*^Input offset current
+R1 1 3 250K
+R2 3 2 250K
+I1 4 50 100U
+R3 5 99 517
+R4 6 99 517
+Q1 5 2 4 QX
+Q2 6 7 4 QX
+*Fp2=2.55 MHz
+C4 5 6 60.3614P
+*
+***********COMMON MODE EFFECT***********
+*
+I2 99 50 1.6MA
+*^Quiescent supply current
+EOS 7 1 POLY(1) 16 49 1E-3 1
+*Input offset voltage.^
+R8 99 49 40K
+R9 49 50 40K
+*
+*********OUTPUT VOLTAGE LIMITING********
+V2 99 8 1.63
+D1 9 8 DX
+D2 10 9 DX
+V3 10 50 1.63
+*
+**************SECOND STAGE**************
+*
+EH 99 98 99 49 1
+G1 98 9 5 6 2.1E-3
+*Fp1=5 Hz
+R5 98 9 95.493MEG
+C3 98 9 333.33P
+*
+***************POLE STAGE***************
+*
+*Fp=30 MHz
+G3 98 15 9 49 1E-6
+R12 98 15 1MEG
+C5 98 15 5.3052E-15
+*
+*********COMMON-MODE ZERO STAGE*********
+*
+*Fpcm=300 Hz
+G4 98 16 3 49 3.1623E-8
+L2 98 17 530.5M
+R13 17 16 1K
+*
+**************OUTPUT STAGE**************
+*
+F6 50 99 POLY(1) V6 450U 1
+E1 99 23 99 15 1
+R16 24 23 25
+D5 26 24 DX
+V6 26 22 0.65V
+R17 23 25 25
+D6 25 27 DX
+V7 22 27 0.65V
+V5 22 21 0.18V
+D4 21 15 DX
+V4 20 22 0.18V
+D3 15 20 DX
+L3 22 28 100P
+RL3 22 28 100K
+*
+***************MODELS USED**************
+*
+.MODEL DX D(IS=1E-15)
+.MODEL QX NPN(BF=625)
+*
+.ENDS
+*$
diff --git a/webtronix_server/spice/models.lib b/webtronix_server/spice/models.lib
new file mode 100755
index 0000000..39488f4
--- /dev/null
+++ b/webtronix_server/spice/models.lib
@@ -0,0 +1,72 @@
+
+.model 1n4007 D(IS=3.872n RS=1.66E-02 N=1.776 XTI=3.0 EG=1.110
++ CJO=1.519E-11 M=0.3554 VJ=0.5928 FC=0.5 ISR=1.356E-09
++ NR=2.152 BV=1000.0 IBV=1.0E-03 Tt=4u)
+
+.model 1n4148 D(Is=5.84n N=1.94 Rs=.7017 Ikf=44.17m Xti=3 Eg=1.11 Cjo=.95p
++ M=.55 Vj=.75 Fc=.5 Isr=11.07n Nr=2.088 Bv=100 Ibv=100u Tt=11.07n)
+
+.MODEL 1N34A D(bv=75 cjo=0.5e-12 eg=0.67 ibv=18e-3
++ is=2e-7 rs=7 n=1.3 vj=0.1 m=0.27 )
+
+
+.MODEL 1N5711 D IS=5.5987E-9 N=1.0023 RS=30.053 IKF=19.036 CJO=1.7605E-12
++ M=.20029 VJ=.3905 ISR=24.229E-9 NR=4.1695 FC=0.5 TT=0 XTI=2
+* $
+
+.MODEL mmsd301t1 d
++IS=7.59492e-08 RS=4.93246 N=1.53455 EG=0.608881
++XTI=4 BV=30 IBV=1e-05 CJO=2.26925e-12
++VJ=0.4 M=0.260918 FC=0.5 TT=2.98638e-09
++KF=0 AF=1
+
+.model 2N2222 NPN(IS=14.34F XTI=3 EG=1.11 VAF= 74.03 BF=255.9
++ NE=1.307 ISE=14.34F IKF=.2847 XTB=1.5 BR=6.092 NC=2
++ ISC=0 IKR=0 RC=1 CJC=7.306P MJC=.3416 VJC=.75 FC=.5
++ CJE=22.01P MJE=.377 VJE=.75 TR=46.91N TF=411.1P ITF=.6
++ VTF=1.7 XTF=3 RB=10)
+
+.MODEL 2N2907 PNP (IS=15.294E-15 BF=297.85 VAF=100 IKF=1.6607 ISE=29.577E-15
++ NE=1.5507 BR=476 VAR=100 IKR=2.2270 ISC=7.6418E-9 NC=2.1591 NK=.97918
++ RB=2.4875 RC=.69253 CJE=33.186E-12 VJE=.8716 MJE=.40799 CJC=15.649E-12
++ VJC=.56868 MJC=.3619 TF=456.18E-12 XTF=22.393 VTF=28.493 ITF=.62109
++ TR=10.000E-9 )
+
+.model 2N3904 NPN(Is=6.734f Xti=3 Eg=1.11 Vaf=74.03 Bf=416.4 Ne=1.259
++ Ise=6.734f Ikf=66.78m Xtb=1.5 Br=.7371 Nc=2 Isc=0 Ikr=0 Rc=1
++ Cjc=3.638p Mjc=.3085 Vjc=.75 Fc=.5 Cje=4.493p Mje=.2593 Vje=.75
++ Tr=239.5n Tf=301.2p Itf=.4 Vtf=4 Xtf=2 Rb=10)
+
+
+.model 2n3906 PNP(Is=455.9E-18 Xti=3 Eg=1.11 Vaf=33.6 Bf=204.7 Ise=7.558f
++ Ne=1.536 Ikf=.3287 Nk=.9957 Xtb=1.5 Var=100 Br=3.72
++ Isc=529.3E-18 Nc=15.51 Ikr=11.1 Rc=.8508 Cjc=10.13p Mjc=.6993
++ Vjc=1.006 Fc=.5 Cje=10.39p Mje=.6931 Vje=.9937 Tr=10n Tf=181.2p
++ Itf=4.881m Xtf=.7939 Vtf=10 Rb=10)
+
+*2N3055
+*Si 115W 70V 15A 20kHz pkg:TO-3 3,2,1
+
+.MODEL 2N3055 NPN(IS=4.66E-12 BF=360 VAF=100 IKF=0.25 ISE=3.339E-11
++ BR=2 ISC=5E-9 RB=3 IRB=0.001 RBM=0.4 RC=0.04 CJE=5.802E-10 VJE=1.2
++ MJE=0.45 TF=8E-8 XTF=1 ITF=3 PTF=120 CJC=2.121E-10 MJC=0.4 TR=2.55E-6
++ XTB=1 )
+
+
+.MODEL 2N7002 NMOS(LEVEL=3 RS=0.0405 NSUB=1.0E15
++ DELTA=0.1 KAPPA=0.0506 TPG=1 CGDO=6.1716E-10
++ RD=1.22 VTO=2.00 VMAX=1.0E7 ETA=0.0223089
++ NFS=6.6E10 TOX=1.0E-7 LD=1.698E-9 UO=862.425
++ XJ=6.4666E-7 THETA=1.0E-5 CGSO=9.10E-9 L=2.5E-6
++ W=0.5E-2)
+
+
+.model 2n3819 NJF(Beta=1.304m Rd=1 Rs=1 Lambda=2.25m Vto=-3 Is=33.57f
++ Cgd=1.6p Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 Af=1)
+
+.model mpf102 NJF (Beta=1.04m Betatce=-.5 Rd=1 Rs=1 Lambda=2m Vto=-3.41
++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7
++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=11.73E-18
++ Af=1)
+
+
diff --git a/webtronix_server/spice/mymodels.lib b/webtronix_server/spice/mymodels.lib
new file mode 100755
index 0000000..060a231
--- /dev/null
+++ b/webtronix_server/spice/mymodels.lib
@@ -0,0 +1,26 @@
+
+.MODEL 1PS66SB17 D
++ IS = 1.419E-09
++ N = 1.022
++ BV = 6
++ IBV = 2.45E-06
++ RS = 5.112
++ CJO = 7.662E-13
++ VJ = 0.1681
++ M = 0.1995
++ FC = 0.5
++ EG = 0.69
++ XTI = 2
+
+.MODEL 1PS66SB82 D
++ IS = 1.042E-8
++ N = 1.029
++ BV = 17
++ IBV = 0.001
++ RS = 5.567
++ CJO = 9.779E-13
++ VJ = 0.2925
++ M = 0.194
++ FC = 0.5
++ EG = 0.69
++ XTI = 2 \ No newline at end of file
diff --git a/webtronix_server/spice/mysubckt.mod b/webtronix_server/spice/mysubckt.mod
new file mode 100755
index 0000000..022f87a
--- /dev/null
+++ b/webtronix_server/spice/mysubckt.mod
@@ -0,0 +1,131 @@
+* AD8630 SPICE Macro-model
+* Description: Amplifier
+* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 4X
+* Developed by: RM / ADSiv
+* Revision History: 08/10/2012 - Updated to new header style
+* 1.0 (07/2010)
+* Copyright 2010, 2012 by Analog Devices
+*
+* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
+* indicates your acceptance of the terms and provisions in the License Statement.
+*
+* BEGIN Notes:
+*
+* Not Modeled:
+*
+* Parameters modeled include:
+*
+* END Notes
+*
+* Node Assignments
+* noninverting input
+* | inverting input
+* | | positive supply
+* | | | negative supply
+* | | | | output
+* | | | | |
+* | | | | |
+.SUBCKT AD8630 1 2 99 50 45
+*
+* INPUT STAGE
+*
+M1 4 7 8 8 PIX L=1E-6 W=174.1E-6
+M2 6 2 8 8 PIX L=1E-6 W=174.1E-6
+M3 11 7 10 10 NIX L=1E-6 W=174.1E-6
+M4 12 2 10 10 NIX L=1E-6 W=174.1E-6
+RC1 4 14 0.001E+3
+RC2 6 16 0.001E+3
+RC3 17 11 0.001E+3
+RC4 18 12 0.001E+3
+RC5 14 50 6E+3
+RC6 16 50 6E+3
+RC7 99 17 6E+3
+RC8 99 18 6E+3
+*Set teh secondary pole at 17MHz using c1,c2 and RC5..
+C1 14 16 5.40E-12
+C2 17 18 5.40E-12
+I1 99 8 100E-6
+I2 10 50 100E-6
+V1 99 9 0.3
+V2 13 50 0.3
+D1 8 9 DX
+D2 13 10 DX
+* POLY font rewritten to make it work under gnucap
+* EOS 7 1 POLY(3) (22,98) (73,98) (81,98) 1E-6 1 1 1
+EOS1 7 1 22 98 .5
+EOS2 7 1 73 98 .5
+EOS3 1 1 81 98 .5
+
+
+
+IOS 1 2 25E-12
+*
+* CMRR 120dB, ZERO AT 20Hz
+*
+ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
+RCM1 21 22 50E+6
+CCM1 21 22 159E-12
+RCM2 22 98 50
+*
+* PSRR=115dB, ZERO AT 20Hz
+*
+RPS1 70 0 1E+6
+RPS2 71 0 1E+6
+CPS1 99 70 1E-5
+CPS2 50 71 1E-5
+EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
+RPS3 72 73 28.9E+6
+CPS3 72 73 .25E-9
+RPS4 73 98 40
+*
+* VOLTAGE NOISE REFERENCE OF 20nV/rt(Hz)
+*
+VN1 80 98 0
+RN1 80 98 16.45E-3
+HN 81 98 VN1 20
+RN2 81 98 1
+*
+* INTERNAL VOLTAGE REFERENCE
+*
+EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5
+GSY 99 50 (99,50) 44E-6
+EVP 97 98 (99,50) 0.5
+EVN 51 98 (50,99) 0.5
+*
+* LHP ZERO AT 17MHz, POLE AT 50.3MHz
+*
+E1 32 98 POLY(2) (4,6) (11,12) 0 .6689 .6689
+R2 32 33 3.164E+3
+R3 33 98 9.362E+3
+C3 32 33 1E-12
+*
+* GAIN STAGE
+*
+G1 98 30 (33,98) 25E-6
+R1 30 98 2.46E+9
+CF 45 30 12.4E-12
+D3 30 97 DX
+D4 51 30 DX
+*
+* OUTPUT STAGE
+*
+M5 45 46 99 99 POX L=1E-6 W=1.47E-3
+M6 45 47 50 50 NOX L=1E-6 W=1.90E-3
+EG1 99 46 POLY(1) (98,30) 0.5303 1
+EG2 47 50 POLY(1) (30,98) 0.5058 1
+*
+* MODELS
+*
+.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0)
+.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0)
+.MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01)
+.MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01)
+.MODEL DX D(IS=1E-14,RS=5)
+.ENDS AD8630
+*
+
+
+
+
+
+
diff --git a/webtronix_server/spice/ne555.mod b/webtronix_server/spice/ne555.mod
new file mode 100755
index 0000000..f5c68b8
--- /dev/null
+++ b/webtronix_server/spice/ne555.mod
@@ -0,0 +1,686 @@
+* IRTCLIB1.txt
+* Models for PSpice
+* Intuitive Research and Technology Corp
+* www.irtc-hq.com
+* Copyright 2007 - All Rights Reserved
+*
+* Models included:
+* UC1845 - UC1845 PWM controller
+* 555 - 555 timer - fixes problems with PSpice library model
+* HCPL5201 - Optocoupler
+* HCPL5230 - Dual Optocoupler
+* UC1707 - Dual Channel Power Driver IC
+* MAX707 - µP Supervisory IC
+* TC4427 - Buffer/driver
+* UCC1802 - PWM controller IC
+* UCC1804 - PWM controller IC
+* D1N3611 - 1N3611 diode
+* OPAMPIB - near-ideal op amp macromodel
+* OPAMPIC - near-ideal op amp macromodel
+* BUFST - Schmitt trigger digital buffer macromodel
+* VREGD - 3-terminal ideal regulator macromodel
+* COMPI - near-ideal comparator
+* ILOADB - current load macromodel
+* EILIM - voltage source with current limit macromodel
+*
+* UC1845 PWM controller IC *
+* connections: pins 1 - 8 sequential (8-pin pkge.)
+.SUBCKT UC1845 COMP VFB CS RTCT GND OUT VCC VREF
+R_R1 VCC GND 1.4k
+D_D7 GND VCC DZ34
+R_R12 VCC $N_0001 10K
+R_R13 $N_0001 VREF 60K
+V_V1 $N_0002 GND DC 7.22V
+X_U21 $N_0003 $N_0004 $G_DPWR $G_DGND BUFST
+X_U7 $N_0004 $N_0005 $G_DPWR $G_DGND INV
+R_R8 $N_0006 0 1MEG
+C_C1 $N_0006 0 500p
+R_R7 $N_OUTST $N_0006 100
+D_D6 $N_0007 $N_0008 D1N3611
+D_D8 GND $N_0009 DZ1
+D_D5 COMP $N_0007 D1N3611
+D_D9 VCC $N_0010 D1N3611
+E_E2 $N_0033 GND VREF GND 0.5
+V_V5 $N_5V 0 DC 5V
+V_V5G $N_5VG GND DC 5.1V
+X_U24 $N_0011 $N_0012 $G_DPWR $G_DGND BUFST
+V_VOH $N_0013 GND DC 2.5V
+X_U25 $N_0014 $N_0015 $G_DPWR $G_DGND BUFST
+E_E1 $N_0003 0 VREF GND 1
+V_VOL $N_0016 GND DC 0.8V
+R_RO4 RTCT $N_0017 300
+C_C2 $N_0012 0 1p IC=4V
+X_U17 $N_0018 $N_0019 $G_DPWR $G_DGND BUFST
+C_C3 $N_0019 0 1p IC=4V
+X_U26 $N_0001 $N_0002 $N_5VG GND VREF OPAMPIB PARAMS: VR=0.1
+X_U27 $N_0016 RTCT $N_5V 0 $N_0011 OPAMPIB PARAMS: VR=0.1
+X_U28 RTCT $N_0013 $N_5V 0 $N_0014 OPAMPIB PARAMS: VR=0.1
+X_U30 CS $N_0009 $N_5V 0 $N_0018 OPAMPIB PARAMS: VR=0.1
+X_U6 $N_0005 $N_0020 $N_0021 $N_0022 $N_OUTST $G_DPWR $G_DGND OR4
+X_U15 $D_HI $D_LO $N_0019 $N_0020 $N_0025 $N_0022 $G_DPWR $G_DGND
++ DLATRSH
+X_U31 $N_0026 $N_0020 $G_DPWR $G_DGND BUFST
+X_UO3 $D_HI $D_LO $N_0012 $N_0015 $N_0026 $N_0029 $G_DPWR $G_DGND
++ DLATRSH
+C_C4 $N_0030 0 1p IC=4V
+R_R14 $N_0030 0 1k
+X_U32 $D_HI $N_0020 $N_0030 $N_0021 $N_0032 $G_DPWR $G_DGND TFFRH
+R_U33_Rp $N_5VG GND 20K
+R_U33_RI1 $N_0033 0 1G
+R_U33_RI2 VFB 0 1G
+X_U33_H2 $N_0034 0 $N_0035 0 UC1845_H2
+C_U33_Cc $N_0034 $N_0036 1000p
+E_U33_ABM45 $N_0036 0 VALUE { ((V($N_5VG,GND)-0.2)/{PI})*ATAN(4714*
++ {PI}*V($N_0035,0)/(V($N_5VG,GND)-0.2))+(V($N_5VG)+V(GND))/2 }
+R_U33_Ro $N_0036 COMP 20
+G_U33_ABM2I1 $N_0034 0 VALUE { LIMIT(7m*V($N_0033,VFB),-1m,1m) }
+R_R4 $N_0008 $N_0009 10K
+R_R5 $N_0009 GND 5K
+X_SO1 $N_0026 0 $N_0017 GND UC1845_SO1
+X_S5 $N_0006 0 OUT GND UC1845_S5
+X_S6 $N_0006 0 $N_0010 OUT UC1845_S6
+.ENDS UC1845
+*
+.subckt UC1845_H2 1 2 3 4
+H_H2 3 4 VH_H2 -100
+VH_H2 1 2 0V
+.ends UC1845_H2
+*
+.subckt UC1845_SO1 1 2 3 4
+S_SO1 3 4 1 2 SW2ONA
+RS_SO1 1 2 1G
+.ends UC1845_SO1
+*
+.subckt UC1845_S5 1 2 3 4
+S_S5 3 4 1 2 SW2ONA
+RS_S5 1 2 1G
+.ends UC1845_S5
+*
+.subckt UC1845_S6 1 2 3 4
+S_S6 3 4 1 2 SW2OFFA
+RS_S6 1 2 1G
+.ends UC1845_S6
+*
+* 555 timer IC *
+* connections: pins 1 - 8 sequential (8-pin pkge.)
+.SUBCKT 555 GND TRIG OUT RES CTRL THR DIS VCC
+R_R2 CTRL $N_0001 5K
+R_R3 $N_0001 GND 5K
+R_R1 VCC CTRL 5K
+V_V5 $N_5V 0 DC 5V
+X_U1 THR CTRL $N_5V 0 $N_0002 OPAMPIB PARAMS: VR=0.1
+X_U2 $N_0001 TRIG $N_5V 0 $N_0003 OPAMPIB PARAMS: VR=0.1
+E_E1 $N_0004 0 RES GND 1
+X_U3 $N_0002 $N_0005 $G_DPWR $G_DGND BUFST
+X_U4 $N_0003 $N_0006 $G_DPWR $G_DGND BUFST
+X_U5 $N_0004 $N_0007 $G_DPWR $G_DGND BUFST
+X_U6 $N_0007 $N_0008 $G_DPWR $G_DGND INV
+X_U7 $N_0005 $N_0008 $N_0009 $G_DPWR $G_DGND OR2
+X_U8 $D_HI $D_LO $N_0006 $N_0009 $N_0012 $N_0013 $G_DPWR $G_DGND
++ DLATRSH
+C_C1 $N_0009 0 1p IC=4V
+R_R4 $N_0012 $N_0014 100
+R_R5 $N_0014 0 1MEG
+C_C2 $N_0014 0 500p
+D_D1 VCC $N_0015 D1N4148
+C_C4 $N_0015 OUT 1p
+C_C5 OUT GND 1p
+R_R6 $N_0012 $N_0016 100
+R_R7 $N_0016 0 1MEG
+C_C3 $N_0016 0 100p
+C_C6 DIS GND 1p
+X_S1 $N_0014 0 $N_0015 OUT 555_S1
+X_S2 $N_0014 0 OUT GND 555_S2
+X_S3 $N_0016 0 DIS GND 555_S3
+.ENDS 555
+*
+.subckt 555_S1 1 2 3 4
+S_S1 3 4 1 2 SW2OFFA
+RS_S1 1 2 1G
+.ends 555_S1
+*
+.subckt 555_S2 1 2 3 4
+S_S2 3 4 1 2 SW2ONA
+RS_S2 1 2 1G
+.ends 555_S2
+*
+.subckt 555_S3 1 2 3 4
+S_S3 3 4 1 2 SW2ONA
+RS_S3 1 2 1G
+.ends 555_S3
+*
+.PARAM PI=3.1416
+*
+* OPAMPIB near-ideal op amp *
+* connections: non-inverting input
+* | inverting input
+* | | positive power supply
+* | | | negative power supply
+* | | | | output
+* | | | | |
+.SUBCKT OPAMPIB 1 2 3 4 5 PARAMS: VR=1
+.PARAM AV=10K ; Open-loop gain
+* VR = Rail-to-output voltage difference
+* OUTPUT={(K2*ATAN(K1*V(1,2)))+VOFF}
+* K2={(V(3)-V(4)-2*VR)/PI}, K1={AV/K2}, VOFF={(V(3)+V(4))/2}
+Ri1 1 0 100Meg
+Ri2 2 0 100Meg
+Eo 6 0 VALUE={((V(3,4)-2*VR)/PI)*
++ ATAN(AV*PI*V(1,2)/(V(3,4)-2*VR))+(V(3)+V(4))/2}
+Ro 6 5 10
+Co 5 0 5p
+Rp 3 4 50K
+.ENDS OPAMPIB
+*
+* OPAMPIC near-ideal op amp *
+* connections: non-inverting input
+* | inverting input
+* | | positive power supply
+* | | | negative power supply
+* | | | | output
+* | | | | |
+.SUBCKT OPAMPIC 1 2 3 4 5 PARAMS: VRP=1 VRN=1 AV=10K
+* VRP = Positive rail-to-output voltage difference
+* VRN = Negative rail-to-output voltage difference
+* AV = Open-loop gain
+* OUTPUT={(K2*ATAN(K1*V(1,2)))+VOFF}
+* K2={(V(3)-V(4)-VRP-VRN)/PI}, K1={AV/K2}
+* VOFF={(V(3)+V(4)-VRP+VRN)/2}
+Ri1 1 0 100Meg
+Ri2 2 0 100Meg
+Ci1 1 0 5p
+Ci2 2 0 5p
+Eo 6 0 VALUE={((V(3,4)-VRP-VRN)/PI)*
++ ATAN(AV*PI*V(1,2)/(V(3,4)-VRP-VRN))+(V(3)+V(4)-VRP+VRN)/2}
+Ro 6 5 10
+Co 5 0 5p
+Rp 3 4 50K
+.ENDS OPAMPIC
+*
+* SCHMITT TRIGGER BUFFER *
+.SUBCKT BUFST I0 O
++ optional: DPWR=$G_DPWR DGND=$G_DGND
+U1 BUF
++ DPWR DGND
++ I0 O
++ D_DEF_ST IO_DEF_ST
+.MODEL D_DEF_ST UGATE
+.MODEL IO_DEF_ST UIO (
++ AtoD1="AtoD_STD_ST" AtoD2="AtoD_STD_ST"
++ AtoD3="AtoD_STD_ST" AtoD4="AtoD_STD_ST")
+.ENDS BUFST
+*
+.MODEL SW2ONA VSWITCH(RON=0.01 ROFF=1E7 VON=2.5 VOFF=1.5)
+*
+.MODEL SW2OFFA VSWITCH(RON=0.01 ROFF=1E7 VON=1.5 VOFF=2.5)
+*
+.MODEL DZ1 D(BV=1 IBV=100u)
+*
+.MODEL DZ34 D(BV=34 IBV=100u)
+*
+.MODEL DZ13P5 D(BV=13.5 IBV=100u)
+*
+.MODEL D1N3611 D
++ IS=159.8E-9
++ N=1.797
++ RS=.1693
++ CJO=1.000E-12
++ M=.3333
++ VJ=.75
++ ISR=21.76E-9
++ BV=240
++ IBV=100.0E-6
++ TT=5.000E-9
+*
+* HCPL5201 Optocoupler *
+.SUBCKT HCPL5201 DP DN VCC GND OUT
+X_H1 $N_0001 DN $N_0002 GND HCPL5201_H1
+R_R1a $N_0002 $N_0003 1K
+C_C1 $N_0004 GND 140p
+D_D1 DP $N_0001 DHCPL5230
+R_R1b $N_0003 $N_0004 1K
+D_D1Z GND $N_0003 D5D
+R_RFB1 $N_0004 OUT 60K
+V_VREF $N_0005 GND DC 2.5V
+X_U1 $N_0004 $N_0005 VCC GND OUT OPAMPIC PARAMS: VRP=1.7 VRN=0.4
++ AV=1K
+R_RP GND VCC 1600
+.ENDS HCPL5201
+*
+.subckt HCPL5201_H1 1 2 3 4
+H_H1 3 4 VH_H1 5K
+VH_H1 1 2 0V
+.ends HCPL5201_H1
+*
+.MODEL DHCPL5230 D
++ IS=230.71E-24
++ N=1.1544
++ RS=1.0000E-3
++ EG=1.4200
++ CJO=20.0000E-12
++ M=.3333
++ VJ=.75
++ ISR=100.00E-12
++ NR=10
++ BV=10
++ IBV=100.00E-6
++ TT=5.0000E-9
+*
+.MODEL D5D D(BV=5 IBV=.1m)
+*
+* HCPL5230 Optocoupler *
+.SUBCKT HCPL5230 D1P D1N D2P D2N VCC GND OUT1 OUT2
+X_H1 $N_0001 D1N $N_0002 GND HCPL5230_H1
+X_H2 $N_0003 D2N $N_0004 GND HCPL5230_H2
+V_VREF $N_0005 GND DC 2.5V
+R_R1a $N_0002 $N_0006 1K
+R_R2a $N_0004 $N_0007 1K
+C_C1 $N_0008 GND 140p
+C_C2 $N_0009 GND 140p
+D_D1 D1P $N_0001 DHCPL5230
+D_D2 D2P $N_0003 DHCPL5230
+X_U1 $N_0008 $N_0005 VCC GND OUT1 OPAMPIC PARAMS: VRP=1.7 VRN=0.4
++ AV=1K
+X_U2 $N_0009 $N_0005 VCC GND OUT2 OPAMPIC PARAMS: VRP=1.7 VRN=0.4
++ AV=1K
+R_R1b $N_0006 $N_0008 1K
+R_R2b $N_0007 $N_0009 1K
+D_D2Z GND $N_0007 D5D
+D_D1Z GND $N_0006 D5D
+R_RFB1 $N_0008 OUT1 60K
+R_RFB2 $N_0009 OUT2 60K
+R_RP GND VCC 800
+.ENDS HCPL5230
+*
+.subckt HCPL5230_H1 1 2 3 4
+H_H1 3 4 VH_H1 5K
+VH_H1 1 2 0V
+.ends HCPL5230_H1
+*
+.subckt HCPL5230_H2 1 2 3 4
+H_H2 3 4 VH_H2 5K
+VH_H2 1 2 0V
+.ends HCPL5230_H2
+*
+* UC1707 Dual Channel Power Driver IC *
+* connections: pins 1 - 16 sequential (exc. GND) (16-pin pkge.)
+.SUBCKT UC1707 BI BNI LD GND OUTA SD VC STOPI STOPNI OUTB VIN ANI AI
+E_E3 $N_0001 0 BNI GND 1
+E_E4 $N_0002 0 BI GND 1
+X_U5 $N_0001 $N_0003 $G_DPWR $G_DGND BUFST
+X_U6 $N_0002 $N_0004 $G_DPWR $G_DGND BUFST
+X_U8 $N_0003 $N_0005 $G_DPWR $G_DGND INV
+V_V1 $N_0006 STOPI DC 0.13
+R_R1 $N_0007 SD 1k
+C_C1 $N_0008 0 1p IC=4V
+X_U11 $N_0009 $N_0010 $G_DPWR $G_DGND BUFST
+X_U10 $D_HI $D_LO $N_0008 $N_0010 $N_0013 $N_0014 $G_DPWR $G_DGND
++ DLATRSH
+R_R4 $N_0015 0 1MEG
+C_C3 $N_0015 0 500p
+X_U16 $N_0016 $N_0013 $N_0017 $G_DPWR $G_DGND OR2
+X_U7 $N_0005 $N_0004 $N_0016 $G_DPWR $G_DGND OR2
+R_R5 $N_0017 $N_0015 100
+E_E1 $N_0018 0 ANI GND 1
+E_E2 $N_0019 0 AI GND 1
+X_U1 $N_0018 $N_0020 $G_DPWR $G_DGND BUFST
+X_U2 $N_0019 $N_0021 $G_DPWR $G_DGND BUFST
+X_U3 $N_0020 $N_0022 $G_DPWR $G_DGND INV
+R_R2 $N_0023 0 1MEG
+C_C2 $N_0023 0 500p
+X_U15 $N_0024 $N_0013 $N_0025 $G_DPWR $G_DGND OR2
+R_R3 $N_0025 $N_0023 100
+X_U4 $N_0022 $N_0021 $N_0024 $G_DPWR $G_DGND OR2
+R_R6 $N_5V $N_0007 5k
+X_U9 $N_0026 $N_0008 $G_DPWR $G_DGND BUFST
+E_E6 $N_0009 0 SD GND 1
+R_R8 $N_5V LD 30k
+X_S2 $N_0023 0 $N_0027 OUTA UC1707_S2
+X_S1 $N_0023 0 OUTA GND UC1707_S1
+X_S3 $N_0015 0 OUTB GND UC1707_S3
+X_S4 $N_0015 0 $N_0028 OUTB UC1707_S4
+X_U19 VIN $N_5V GND VREGD PARAMS: VO=5 IQ=10m VD=0.5
+E_E5 $N_0026 0 LD GND 1
+X_U20 STOPNI $N_0006 $N_5V GND $N_0007 GND COMPI
+D_D3 VC $N_0027 D1N4148
+D_D4 VC $N_0028 D1N4148
+.ENDS UC1707
+*
+.subckt UC1707_S2 1 2 3 4
+S_S2 3 4 1 2 SW2OFFA
+RS_S2 1 2 1G
+.ends UC1707_S2
+*
+.subckt UC1707_S1 1 2 3 4
+S_S1 3 4 1 2 SW2ONA
+RS_S1 1 2 1G
+.ends UC1707_S1
+*
+.subckt UC1707_S3 1 2 3 4
+S_S3 3 4 1 2 SW2ONA
+RS_S3 1 2 1G
+.ends UC1707_S3
+*
+.subckt UC1707_S4 1 2 3 4
+S_S4 3 4 1 2 SW2OFFA
+RS_S4 1 2 1G
+.ends UC1707_S4
+*
+* TC4427 - Buffer/driver *
+.SUBCKT TC4427 IN OUT VDD GND
+R_R3 $N_0001 GND 1Meg
+R_R1 $N_0002 OUT 7
+R_R2 IN $N_0001 100
+C_C1 $N_0001 GND 400p
+X_S1 $N_0001 GND VDD $N_0002 TC4427_S1
+X_S2 $N_0001 GND $N_0002 GND TC4427_S2
+.ENDS TC4427
+*
+.subckt TC4427_S1 1 2 3 4
+S_S1 3 4 1 2 SW2ONA
+RS_S1 1 2 1G
+.ends TC4427_S1
+*
+.subckt TC4427_S2 1 2 3 4
+S_S2 3 4 1 2 SW2OFFA
+RS_S2 1 2 1G
+.ends TC4427_S2
+*
+* 3-TERMINAL REGULATOR MACROMODEL WITH OUTPUT VOLTAGE PARAMETERS
+* CONNECTIONS: INPUT
+* | OUTPUT
+* | | RTN
+* | | | OUTPUT VOLTAGE
+* | | | | QUIESCENT CURRENT
+* | | | | | dropout voltage
+* | | | | | |
+.SUBCKT VREGD 1 2 3 PARAMS: VO=5 IQ=1m VD=2
+Eo 4 3 VALUE={LIMIT(VO,0,V(1,3)-VD)}
+Rq 2 3 {VO/IQ} ; sets quiescent current
+VS 4 2 0
+Fi 1 3 VS 1
+.ENDS VREGD
+*
+* Macro-model for ideal Comparator with Open Collector Output
+* connections: non-inverting input
+* | inverting input
+* | | positive power supply
+* | | | negative power supply
+* | | | | output
+* | | | | | output rtn
+.SUBCKT COMPI 2 1 3 4 5 6
+.PARAM AV=10K ; Open-loop gain (adjustable)
+.PARAM VR=0.1 ; Rail-to-driver voltage difference (adjustable)
+.PARAM PI=3.1416
+Ri1 1 0 100Meg
+Ri2 2 0 100Meg
+Eo 7 0
++ VALUE={((V(3,4)-2*VR)/PI)*ATAN(AV*PI*V(1,2)/(V(3,4)-2*VR))+(V(3)+V(4))/2}
+Ro 7 8 1K
+Qo 5 8 6 Q2N2222
+Rp 3 4 50K
+.ENDS COMPI
+*
+* MAX707 µP Supervisory IC *
+* connections: pins 1 - 5, 7, 8 sequential (8-pin pkge.)
+.SUBCKT MAX707 MRn VCC GND PFI PFOn RESn RES
+R_R1 VCC MRn 20K
+V_V1 $N_0001 GND DC 4.65
+X_U1 $N_0002 $N_0001 $N_5V 0 $N_0003 OPAMPIB PARAMS: VR=0.1
+R_R5 VCC $N_0002 10K
+R_R6 $N_0002 $N_0003 1.2MEG
+X_S1 $N_0004 0 $N_0005 0 MAX707_S1
+V_V8 $N_0006 0 DC 6.32
+X_U29 $N_0005 $N_0006 $N_5V 0 $N_0015 OPAMPIB PARAMS: VR=0.1
+R_U1_R1 $N_0011 0 1MEG
+C_U1_C1 $N_0011 0 500p
+R_U1_R2 $N_0015 $N_0011 100
+X_U1_S2 $N_0011 0 RESn GND MAX707_S1
+D_U1_D2 $N_0012 $N_0013 D1N3611
+X_U1_S1 $N_0011 0 $N_0013 RESn MAX707_S2
+D_U1_D1 VCC $N_0012 D1N3611
+X_U2_S1 $N_0014 0 RES GND MAX707_S2
+R_U2_R1 $N_0014 0 1MEG
+C_U2_C1 $N_0014 0 500p
+R_U2_R2 $N_0015 $N_0014 100
+D_U2_D1 VCC $N_0016 D1N3611
+X_U2_S2 $N_0014 0 $N_0017 RES MAX707_S1
+D_U2_D2 $N_0016 $N_0017 D1N3611
+V_V2 $N_0007 GND DC 1.25
+R_U3_R1 $N_0018 0 1MEG
+C_U3_C1 $N_0018 0 500p
+R_U3_R2 $N_0019 $N_0018 100
+X_U3_S2 $N_0018 0 PFOn GND MAX707_S1
+D_U3_D2 $N_0020 $N_0021 D1N3611
+X_U3_S1 $N_0018 0 $N_0021 PFOn MAX707_S2
+D_U3_D1 VCC $N_0020 D1N3611
+X_U2 PFI $N_0007 $N_5V 0 $N_0019 OPAMPIB PARAMS: VR=0.1
+V_V7 $N_5V 0 DC 5
+V_V9 $N_10V 0 DC 10
+R_R7 $N_10V $N_0005 10K
+X_U16 $N_0008 $N_0009 $G_DPWR $G_DGND BUFST
+X_U17 $N_0003 $N_0010 $G_DPWR $G_DGND BUFST
+X_U27 $N_0009 $N_0010 $N_0004 $G_DPWR $G_DGND AND2
+E_E1 $N_0008 0 MRn GND 1
+R_XR1 RESn 0 1E24
+R_XR2 RES 0 1E24
+R_XR3 PFOn 0 1E24
+R_XR4 MRn 0 1E24
+R_R8 VCC GND 100K
+C_C1 $N_0005 0 20u IC=9.9V
+.ENDS MAX707
+*
+.subckt MAX707_S1 1 2 3 4
+S_S1 3 4 1 2 SW2OFFA
+RS_S1 1 2 1G
+.ends MAX707_S1
+*
+.subckt MAX707_S2 1 2 3 4
+S_S2 3 4 1 2 SW2ONA
+RS_S2 1 2 1G
+.ends MAX707_S2
+*
+* UCC1802 PWM controller IC *
+* connections: pins 1 - 8 sequential (8-pin pkge.)
+.SUBCKT UCC1802 COMP FB CS RC GND OUT VCC REF
+R_RP VCC GND 20K
+R_R3 $N_0002 $N_0001 20k
+R_R4 $N_0001 GND 20k
+R_RO1 $N_OUTD $N_0003 100
+R_RO2 $N_0003 0 1MEG
+C_CO $N_0003 0 500p
+D_DZ1 GND $N_0001 DZ1
+D_DZV GND VCC DZ13P5
+R_RD1 REF $N_REFh 1k
+V_VRVCC $N_0004 GND DC 6.72V
+R_RD2 $N_REFh GND 1k
+X_U10 $N_REF0 $N_0005 $N_0006 $G_DPWR $G_DGND AND2
+V_VROC $N_0007 GND DC 1.5V
+X_U12 $D_HI $D_LO $N_0009 $N_0011 $N_0012 $N_0013 $G_DPWR $G_DGND
++ DLATRSH
+X_U14 $N_0006 $N_0011 $G_DPWR $G_DGND INV
+X_U15 $D_HI $D_LO $N_0009 $N_0016 $N_0017 $N_0018 $G_DPWR $G_DGND
++ DLATRSH
+X_U16 $N_0006 $N_0019 $N_0009 $G_DPWR $G_DGND AND2
+V_VRT1 $N_0020 0 DC 0.5V
+V_VRT2 $N_0021 0 DC 4V
+X_U19 $N_0012 $N_0017 $N_0022 $G_DPWR $G_DGND AND2
+R_RB $N_0022 $N_0023 10K
+Q_QC $N_TSS $N_0023 0 Q2N2222
+C_CTSS $N_TSS 0 1.14uF
+X_U22 $N_REF0 $N_0013 $N_0024 $N_0025 $N_OUTD $G_DPWR $G_DGND AND4
+D_D1 COMP $N_0002 D1N3611
+D_DO VCC $N_0026 D1N3611
+X_U23 $D_LO $D_LO $N_OUTD $N_0031 $N_0032 $G_DPWR $G_DGND 74121
++ PARAMS: PULSE=140ns IO_LEVEL=0 MNTYMXDLY=0
+V_V5 $N_5V 0 DC 5V
+E_E1 $N_REF0 0 REF GND 1
+V_VREF $N_0034 GND DC 5.125V
+E_ETSS $N_TSSG GND $N_TSS 0 1
+C_CCS $N_CSBL GND 0.5p
+X_U7 $D_HI $D_LO $N_0036 $N_0038 $N_0025 $N_0039 $G_DPWR $G_DGND
++ DLATRSH
+X_U8 $N_0040 $N_0004 $N_0034 GND REF OPAMPIC PARAMS: VRP=0.1 VRN=0.1
++ AV=100K
+X_U11 $N_0007 $N_CSBL $N_5V 0 $N_0005 OPAMPIC PARAMS: VRP=0.1
++ VRN=0.1 AV=100K
+X_U17 $N_0020 $N_TSS $N_5V 0 $N_0019 OPAMPIC PARAMS: VRP=0.1
++ VRN=0.1 AV=100K
+X_U18 $N_TSS $N_0021 $N_5V 0 $N_0016 OPAMPIC PARAMS: VRP=0.1
++ VRN=0.1 AV=100K
+X_U2 $N_REFh FB $N_TSSG GND $N_0041 OPAMPIC PARAMS: VRP=0.1 VRN=0.1
++ AV=100K
+X_U3 $N_CSBL $N_0001 $N_5V 0 $N_0042 OPAMPIC PARAMS: VRP=0.1
++ VRN=0.1 AV=100K
+R_R13 VCC $N_0040 10K
+R_R14 $N_0040 REF 11.5K
+X_UO1 RC $N_0043 $N_5V 0 $N_0044 OPAMPIC PARAMS: VRP=0.1 VRN=0.1
++ AV=100K
+V_VOH $N_0043 GND DC 2.5V
+R_RO4 RC $N_0045 125
+V_VOL $N_0046 GND DC 0.2V
+X_EL1 COMP GND $N_0041 GND EILIM PARAMS:ILIMX=0.5m
+X_U31 $N_0038 $N_0024 $G_DPWR $G_DGND INV
+X_U32 $N_0047 $N_0038 $G_DPWR $G_DGND BUFST
+X_U33 $N_0042 $N_0036 $G_DPWR $G_DGND BUFST
+X_SL $N_0003 0 OUT GND UCC1802_SL
+X_SH $N_0003 0 $N_0026 OUT UCC1802_SH
+X_SBL $N_0032 0 CS $N_CSBL UCC1802_SH
+X_SO1 $N_0047 0 $N_0045 GND UCC1802_SH
+X_X1 $N_REF0 $N_TSS ILOADB PARAMS: ID=1mA VD=0.2
+C_C6 $N_0009 0 1p IC=4V
+C_C7 $N_0036 0 1p IC=4V
+C_C8 $N_0048 0 1p IC=4V
+X_UO2 $N_0046 RC $N_5V 0 $N_0048 OPAMPIC PARAMS: VRP=0.1 VRN=0.1
++ AV=100K
+X_UO3 $D_HI $D_LO $N_0048 $N_0044 $N_0047 $N_0051 $G_DPWR $G_DGND
++ DLATRSH
+.ENDS UCC1802
+*
+.subckt UCC1802_SL 1 2 3 4
+S_SL 3 4 1 2 SW2OFFA
+RS_SL 1 2 1G
+.ends UCC1802_SL
+*
+.subckt UCC1802_SH 1 2 3 4
+S_SH 3 4 1 2 SW2ONA
+RS_SH 1 2 1G
+.ends UCC1802_SH
+*
+.subckt ILOADB IN+ IN- PARAMS: ID=1 VD=1
+J1 IN+ IN- IN- ILJ
+.PARAM VTOI={-1*VD}
+.PARAM BETI={ID/(VD*VD)}
+.model ILJ NJF (VTO={VTOI} BETA={BETI})
+.ends ILOADB
+*
+* Voltage Source with Current Limit, with Control Input
+* OUT+
+* | OUT-
+* | | Output Voltage Control +
+* | | | Output Voltage Control -
+* | | | | Limit Current
+* | | | | |
+.SUBCKT EILIM 1 2 5 6 PARAMS: ILIMX=1m
+HS 3 1 VD 1
+ES 3 4 5 6 1 ; Controls Output Voltage
+VS 4 2 0
+DD 10 0 DX
+HD 10 11 POLY(2) VS VL 0 -1MEG -1MEG
+VD 0 11 0
+VL 20 0 0
+IL 0 20 {ILIMX} ; Limit Current
+.MODEL DX D(IS=1E-15)
+.ENDS EILIM
+*
+* UCC1804 PWM controller IC *
+* connections: pins 1 - 8 sequential (8-pin pkge.)
+.SUBCKT UCC1804 COMP FB CS RC GND OUT VCC REF
+R_RP VCC GND 20K
+R_R3 $N_0002 $N_0001 20k
+R_R4 $N_0001 GND 20k
+R_RO1 $N_OUTD $N_0003 100
+R_RO2 $N_0003 0 1MEG
+C_CO $N_0003 0 500p
+D_DZ1 GND $N_0001 DZ1
+D_DZV GND VCC DZ13P5
+R_RD1 REF $N_REFh 1k
+V_VRVCC $N_0004 GND DC 6.72V
+R_RD2 $N_REFh GND 1k
+X_U10 $N_REF0 $N_0005 $N_0006 $G_DPWR $G_DGND AND2
+V_VROC $N_0007 GND DC 1.5V
+X_U12 $D_HI $D_LO $N_0009 $N_0011 $N_0012 $N_0013 $G_DPWR $G_DGND
++ DLATRSH
+X_U14 $N_0006 $N_0011 $G_DPWR $G_DGND INV
+X_U16 $N_0006 $N_0014 $N_0009 $G_DPWR $G_DGND AND2
+V_VRT1 $N_0015 0 DC 0.5V
+V_VRT2 $N_0016 0 DC 4V
+X_U19 $N_0012 $N_0017 $N_0018 $G_DPWR $G_DGND AND2
+R_RB $N_0018 $N_0019 10K
+Q_QC $N_TSS $N_0019 0 Q2N2222
+C_CTSS $N_TSS 0 1.14uF IC=4
+D_D1 COMP $N_0002 D1N3611
+D_DO VCC $N_0020 D1N3611
+X_U23 $D_LO $D_LO $N_OUTD $N_0025 $N_0026 $G_DPWR $G_DGND 74121
++ PARAMS: PULSE=140ns IO_LEVEL=0 MNTYMXDLY=0
+V_V5 $N_5V 0 DC 5V
+E_E1 $N_REF0 0 REF GND 1
+V_VREF $N_0028 GND DC 5.125V
+E_ETSS $N_TSSG GND $N_TSS 0 1
+C_CCS $N_CSBL GND 0.5p
+X_U7 $D_HI $D_LO $N_0030 $N_0032 $N_0033 $N_0034 $G_DPWR $G_DGND
++ DLATRSH
+X_U11 $N_0007 $N_CSBL $N_5V 0 $N_0005 OPAMPIC PARAMS: VRP=0.1
++ VRN=0.1 AV=100K
+X_U17 $N_0015 $N_TSS $N_5V 0 $N_0014 OPAMPIC PARAMS: VRP=0.1
++ VRN=0.1 AV=100K
+X_U18 $N_TSS $N_0016 $N_5V 0 $N_0035 OPAMPIC PARAMS: VRP=0.1
++ VRN=0.1 AV=100K
+X_U3 $N_CSBL $N_0001 $N_5V 0 $N_0036 OPAMPIC PARAMS: VRP=0.1
++ VRN=0.1 AV=100K
+R_R13 VCC $N_0037 10K
+R_R14 $N_0037 REF 11.5K
+X_UO1 RC $N_0038 $N_5V 0 $N_0039 OPAMPIC PARAMS: VRP=0.1 VRN=0.1
++ AV=100K
+V_VOH $N_0038 GND DC 2.5V
+R_RO4 RC $N_0040 125
+X_UO2 $N_0041 RC $N_5V 0 $N_0042 OPAMPIC PARAMS: VRP=0.1 VRN=0.1
++ AV=100K
+V_VOL $N_0041 GND DC 0.2V
+X_UO3 $D_HI $D_LO $N_0042 $N_0039 $N_0045 $N_0046 $G_DPWR $G_DGND
++ DLATRSH
+X_EL1 COMP GND $N_0047 GND EILIM PARAMS:ILIMX=0.5m
+X_U22 $N_REF0 $N_0013 $N_0048 $N_0049 $N_0033 $N_OUTD $G_DPWR
++ $G_DGND AND5
+X_U33 $N_0032 $N_0049 $G_DPWR $G_DGND INV
+X_U34 $N_0036 $N_0030 $G_DPWR $G_DGND BUFST
+X_U35 $N_0045 $N_0032 $G_DPWR $G_DGND BUFST
+X_U8 $N_0037 $N_0004 $N_0028 GND REF OPAMPIC PARAMS: VRP=0.1 VRN=0.1
++ AV=100K
+X_U2 $N_REFh FB $N_TSSG GND $N_0047 OPAMPIC PARAMS: VRP=0.1 VRN=0.1
++ AV=100K
+C_C6 $N_0030 0 1p IC=4V
+C_C7 $N_0042 0 1p IC=4V
+X_U15 $D_HI $D_LO $N_0009 $N_0035 $N_0017 $N_0052 $G_DPWR $G_DGND
++ DLATRSH
+C_C5 $N_0009 0 1p IC=4V
+X_X1 $N_REF0 $N_TSS ILOADB PARAMS: ID=1mA VD=0.2
+X_SL $N_0003 0 OUT GND UCC1804_SL
+X_SH $N_0003 0 $N_0020 OUT UCC1804_SH
+X_U36 $D_HI $N_0032 $N_0053 $N_0048 $N_0055 $G_DPWR $G_DGND TFFRH
+R_R15 $N_0053 0 1k
+C_C8 $N_0053 0 1p IC=4V
+X_SO1 $N_0045 0 $N_0040 GND UCC1804_SH
+X_SBL $N_0026 0 CS $N_CSBL UCC1804_SH
+.ENDS UCC1804
+*
+.subckt UCC1804_SL 1 2 3 4
+S_SL 3 4 1 2 SW2OFFA
+RS_SL 1 2 1G
+.ends UCC1804_SL
+*
+.subckt UCC1804_SH 1 2 3 4
+S_SH 3 4 1 2 SW2ONA
+RS_SH 1 2 1G
+.ends UCC1804_SH
+*$
diff --git a/webtronix_server/spice/tl084.mod b/webtronix_server/spice/tl084.mod
new file mode 100755
index 0000000..4b88d2d
--- /dev/null
+++ b/webtronix_server/spice/tl084.mod
@@ -0,0 +1,53 @@
+* TL084 OPERATIONAL AMPLIFIER "MACROMODEL" SUBCIRCUIT
+* CREATED USING PARTS RELEASE 4.01 ON 06/16/89 AT 13:08
+* (REV N/A) SUPPLY VOLTAGE: +/-15V
+* EDITED TO WORK IN GNUCAP
+* CONNECTIONS: NON-INVERTING INPUT
+* | INVERTING INPUT
+* | | POSITIVE POWER SUPPLY
+* | | | NEGATIVE POWER SUPPLY
+* | | | | OUTPUT
+* | | | | |
+.SUBCKT TL084 1 2 3 4 5
+*
+ C1 11 12 3.498E-12
+ C2 6 7 15.00E-12
+ DC 5 53 DX
+ DE 54 5 DX
+ DLP 90 91 DX
+ DLN 92 90 DX
+ DP 4 3 DX
+
+** POLY font rewritten to make it work under gnucap
+* EGND 99 0 POLY(2) (3,0) (4,0) 0 .5 .5
+ EGND1 99 98 3 0 .5
+ EGND2 98 0 4 0 .5
+* FB 7 99 POLY(5) VB VC VE VLP VLN 0 4.715E6 -5E6 5E6 5E6 -5E6
+ FB1 7 99 VB 4.715E6
+ FB2 7 99 VC -5E6
+ FB3 7 99 VE 5E6
+ FB4 7 99 VLP 5E6
+ FB5 7 99 VLN -5E6
+
+ GA 6 0 11 12 282.8E-6
+ GCM 0 6 10 99 8.942E-9
+ ISS 3 10 DC 195.0E-6
+ HLIM 90 0 VLIM 1K
+ J1 11 2 10 JX
+ J2 12 1 10 JX
+ R2 6 9 100.0E3
+ RD1 4 11 3.536E3
+ RD2 4 12 3.536E3
+ RO1 8 5 150
+ RO2 7 99 150
+ RP 3 4 2.143E3
+ RSS 10 99 1.026E6
+ VB 9 0 DC 0
+ VC 3 53 DC 2.200
+ VE 54 4 DC 2.200
+ VLIM 7 8 DC 0
+ VLP 91 0 DC 25
+ VLN 0 92 DC 25
+.MODEL DX D(IS=800.0E-18)
+.MODEL JX PJF(IS=15.00E-12 BETA=270.1E-6 VTO=-1)
+.ENDS
diff --git a/webtronix_server/spice/ua741.mod b/webtronix_server/spice/ua741.mod
new file mode 100755
index 0000000..15dcf1a
--- /dev/null
+++ b/webtronix_server/spice/ua741.mod
@@ -0,0 +1,58 @@
+* UA741 OPERATIONAL AMPLIFIER "MACROMODEL" SUBCIRCUIT
+* CREATED USING PARTS RELEASE 4.01 ON 07/05/89 AT 09:09
+* (REV N/A) SUPPLY VOLTAGE: +/-15V
+* CONNECTIONS: NON-INVERTING INPUT
+* | INVERTING INPUT
+* | | POSITIVE POWER SUPPLY
+* | | | NEGATIVE POWER SUPPLY
+* | | | | OUTPUT
+* | | | | |
+.SUBCKT UA741 1 2 3 4 5
+*
+ C1 11 12 4.664E-12
+ C2 6 7 20.00E-12
+ DC 5 53 DX
+ DE 54 5 DX
+ DLP 90 91 DX
+ DLN 92 90 DX
+ DP 4 3 DX
+* EGND 99 0 POLY(2) (3,0) (4,0) 0 .5 .5
+* FB 7 99 POLY(5) VB VC VE VLP VLN 0 10.61E6 -10E6 10E6 10E6 -10E6
+* POLY font rewritten to make it work under gnucap
+* egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5
+egnd1 99 98 3 0 .5
+egnd2 98 0 4 0 .5
+* POLY font rewritten to make it work under gnucap
+* fb 7 99 poly(5) vb vc ve vlp vln 0 10.61E6 -10E6 10E6 10E6 -10E6
+ fb1 7 99 vb 10.61E6
+ fb2 7 99 vc -10E6
+ fb3 7 99 ve 10E6
+ fb4 7 99 vlp 10E6
+ fb5 7 99 vln -10E6
+
+
+ GA 6 0 11 12 137.7E-6
+ GCM 0 6 10 99 2.574E-9
+ IEE 10 4 DC 10.16E-6
+ HLIM 90 0 VLIM 1K
+ Q1 11 2 13 QX
+ Q2 12 1 14 QX
+ R2 6 9 100.0E3
+ RC1 3 11 7.957E3
+ RC2 3 12 7.957E3
+ RE1 13 10 2.740E3
+ RE2 14 10 2.740E3
+ REE 10 99 19.69E6
+ RO1 8 5 150
+ RO2 7 99 150
+ RP 3 4 18.11E3
+ VB 9 0 DC 0
+ VC 3 53 DC 2.600
+ VE 54 4 DC 2.600
+ VLIM 7 8 DC 0
+ VLP 91 0 DC 25
+ VLN 0 92 DC 25
+.MODEL DX D(IS=800.0E-18)
+.MODEL QX NPN(IS=800.0E-18 BF=62.50)
+.ENDS
+
generated by cgit (git 2.34.1) at 2024-12-19 18:48:40 +0000