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{
"cells": [
{
"cell_type": "markdown",
"metadata": {},
"source": [
"# Chapter 12: IC logic gates"
]
},
{
"cell_type": "markdown",
"metadata": {},
"source": [
"## Example 12.1: Determine_fan_out_for_DTL_NAND_gate.sce"
]
},
{
"cell_type": "code",
"execution_count": null,
"metadata": {
"collapsed": true
},
"outputs": [],
"source": [
"//Caption: Determine fan out for DTL NAND gate \n",
"//Ex12.1\n",
"clc;\n",
"clear;\n",
"close;\n",
"hfe=20\n",
"Vbe=0.7//Base emitter voltage(in volts)\n",
"R3=6//Resistance(in kilo ohm)\n",
"R2=5//Resistance(in kilo ohm)\n",
"Vcc=5//Supply voltage(in volts)\n",
"R1=2//Resistance(in kilo ohm)\n",
"Vce=0.2//Collector emitter voltage(in volts)\n",
"Vf4=0.7//Diode forward voltage\n",
"Vf5=Vf4\n",
"Vf6=Vf4\n",
"I2=Vbe/R2\n",
"Va=Vf4+Vf5+Vbe\n",
"I1=(Vcc-Va)/R1\n",
"Ib=I1-I2\n",
"Ic1=hfe*Ib\n",
"I3=(Vcc-Vce)/R3\n",
"Iol=Ic1-I3\n",
"R4=R1\n",
"Iil=(Vcc-Vf6)/R4\n",
"fo=Iol/Iil\n",
"disp(fo,'Fan out=')"
]
}
,
{
"cell_type": "markdown",
"metadata": {},
"source": [
"## Example 12.2: Determine_Resistance_to_drive_inputs_of_5_TTL_gates.sce"
]
},
{
"cell_type": "code",
"execution_count": null,
"metadata": {
"collapsed": true
},
"outputs": [],
"source": [
"//Caption:Determine Resistance to drive inputs of 5 TTL gates\n",
"//Ex12.2\n",
"clc;\n",
"clear;\n",
"close;\n",
"Ii=1.6//Maximum input current(in mA)\n",
"Io=16//Maximum output current(in mA)\n",
"Vcc=5//Supply voltage(in volts)\n",
"Vo=0.4//Maximum output voltage(in volts)\n",
"Il=5*Ii\n",
"Irc=Io-Il\n",
"Vrc=(Vcc-Vo)\n",
"Rc=Vrc*1000/Irc\n",
"disp(Rc,'Required resistance(in ohm)=')"
]
}
,
{
"cell_type": "markdown",
"metadata": {},
"source": [
"## Example 12.4: Design_a_interface_circuit_for_CMOS.sce"
]
},
{
"cell_type": "code",
"execution_count": null,
"metadata": {
"collapsed": true
},
"outputs": [],
"source": [
"//Caption:Design a interface circuit for CMOS\n",
"//Ex12.4\n",
"clc; \n",
"clear;\n",
"close;\n",
"Vdd=15//Drain voltage(in volts)\n",
"Rd=1//Drain resistance(in kilo ohm)\n",
"Vcc=5//Supply voltage(in volts)\n",
"Ih=40//Current(in micro ampere)\n",
"hfe=20\n",
"Vce=0.2//Saturated collector emitter voltage(in volts)\n",
"vih=2//High input voltage(in volts)\n",
"il=1.6//Low input current\n",
"Vbe=0.7//Base emitter voltage(in volts)\n",
"Rc=(Vcc-vih)*1000/(2*Ih)\n",
"Ic=((Vcc-Vce)/Rc)+(2*il)\n",
"Ib=Ic/hfe\n",
"R=(Vdd-Vbe)/Ib\n",
"Rb=R-Rd\n",
"disp(Rc,Rb,'Components required to design circuit are resistors Rb and Rc(in kilo ohm)=')"
]
}
],
"metadata": {
"kernelspec": {
"display_name": "Scilab",
"language": "scilab",
"name": "scilab"
},
"language_info": {
"file_extension": ".sce",
"help_links": [
{
"text": "MetaKernel Magics",
"url": "https://github.com/calysto/metakernel/blob/master/metakernel/magics/README.md"
}
],
"mimetype": "text/x-octave",
"name": "scilab",
"version": "0.7.1"
}
},
"nbformat": 4,
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|
