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diff --git a/Switching_And_Finite_Automata_Theory_by_Z_Kohavi/5-Logical_Design.ipynb b/Switching_And_Finite_Automata_Theory_by_Z_Kohavi/5-Logical_Design.ipynb new file mode 100644 index 0000000..78c361c --- /dev/null +++ b/Switching_And_Finite_Automata_Theory_by_Z_Kohavi/5-Logical_Design.ipynb @@ -0,0 +1,252 @@ +{ +"cells": [ + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "# Chapter 5: Logical Design" + ] + }, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 5.1: Odd_Parity_Bit_Generator.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"clc;\n", +"clear;\n", +"//Takes x input and check whether it is valid logic level or not.\n", +"x=input('x = ');\n", +"while(x~=0 & x~=1)\n", +" disp('enter a valid logical level');\n", +" x=input('x = ');\n", +"end\n", +"//Takes y input and check whether it is valid logic level or not.\n", +"y=input('y = ');\n", +"while(y~=0 & y~=1)\n", +" disp('enter a valid logical level');\n", +" y=input('y = ');\n", +"end\n", +"//Takes z input and check whether it is valid logic level or not.\n", +"z=input('z = ');\n", +"while(z~=0 & z~=1)\n", +" disp('enter a valid logical level');\n", +" z=input('z = ');\n", +"end\n", +"p1=bitand(bitand(bitcmp(x,1),bitcmp(y,1)),z);\n", +"p2=bitand(bitand(bitcmp(x,1),y),bitcmp(z,1));\n", +"p3=bitand(bitand(bitcmp(y,1),x),bitcmp(z,1));\n", +"p4=bitand(bitand(x,y),z);\n", +"p=bitor(bitor(p1,p2),bitor(p3,p4));\n", +"disp(p,'The output of the odd parity generator circuit is');\n", +"disp('p= x^y^z+x^yz^+xy^z^+xyz');" + ] + } +, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 5.2: Serial_To_Parallel_converter.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"clc;\n", +"clear;\n", +"//Takes x input and check whether it is valid logic level or not.\n", +"disp('enter the vaLue of input Line & controL signaLs C1 and C2');\n", +"x=input('x = ');\n", +"while(x~=0 & x~=1)\n", +" disp('enter a vaLid LogicaL LeveL');\n", +" x=input('x = ');1\n", +"end\n", +"//Takes C1 input and check whether it is valid logic level or not.\n", +"C1=input('C1 = ');\n", +"while(C1~=0 & C1~=1)\n", +" disp('enter a vaLid LogicaL LeveL');\n", +" C1=input('C1 = ');\n", +"end\n", +"//Takes C2 input and check whether it is valid logic level or not.\n", +"C2=input('C2 = ');\n", +"while(C2~=0 & C2~=1)\n", +" disp('enter a vaLid LogicaL LeveL');\n", +" C2=input('C2 = ');\n", +"end\n", +"disp('-------OUTPUT-------');\n", +"disp(L1=bitand(bitand(bitcmp(C1,1),bitcmp(C2,1)),x),'L1 = ');\n", +"disp(L2=bitand(bitand(bitcmp(C1,1),C2),x),'L2 = ');\n", +"disp(L3=bitand(bitand(C1,bitcmp(C2,1)),x),'L3 = ');\n", +"disp(L4=bitand(bitand(C1,C2),x),'L4 = ');\n", +"disp('L1=xC1^C2^');\n", +"disp('L2=xC1^C2');\n", +"disp('L3=xC1C2^');\n", +"disp('L4=xC1^C2^');" + ] + } +, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 5.3: Transmission_function_for_a_network.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"clc;\n", +"clear;\n", +"//Takes input and check whether it is valid logic level or not.\n", +"w=input('w = ');\n", +"while(w~=0 & w~=1)\n", +" disp('enter a valid logical level');\n", +" w=input('w = ');\n", +"end\n", +"x=input('x = ');\n", +"while(x~=0 & x~=1)\n", +" disp('enter a valid logical level');\n", +" x=input('x = ');\n", +"end\n", +"y=input('y = ');\n", +"while(y~=0 & y~=1)\n", +" disp('enter a valid logical level');\n", +" y=input('y = ');\n", +"end\n", +"z=input('z = ');\n", +"while(z~=0 & z~=1)\n", +" disp('enter a valid logical level');\n", +" z=input('z = ');\n", +"end\n", +"disp('original network x^[((y^z+z^y)w^)+w+y^+x^z^]');\n", +"disp('x^[w^y^z+w^yz^+w+y^+x^z^]');\n", +"disp('x^[y^(w^z+1)+w^yz^+w+x^z^]');\n", +"disp('x^[y^+w+yz^+x^z^]');\n", +"disp('x^[y^+yz^+w+x^z^]');\n", +"disp('x^[y^+z^+x^z^+w]');\n", +"disp('x^[y^+z^+w]');\n", +"//output of the relay network for the inputs given\n", +"disp(p=bitand(bitcmp(x,1),bitor(bitor(bitcmp(y,1),bitcmp(z,1)),w)),'output = ');" + ] + } +, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 5.4: 4_Input_Contact_Network.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"clc;\n", +"clear;\n", +"//Takes input and check whether it is valid logic level or not.\n", +"w=input('w = ');\n", +"while(w~=0 & w~=1)\n", +" disp('enter a valid logical level');\n", +" w=input('w = ');\n", +"end\n", +"x=input('x = ');\n", +"while(x~=0 & x~=1)\n", +" disp('enter a valid logical level');\n", +" x=input('x = ');\n", +"end\n", +"y=input('y = ');\n", +"while(y~=0 & y~=1)\n", +" disp('enter a valid logical level');\n", +" y=input('y = ');\n", +"end\n", +"z=input('z = ');\n", +"while(z~=0 & z~=1)\n", +" disp('enter a valid logical level');\n", +" z=input('z = ');\n", +"end\n", +"disp('We have 4 relays W,X,Y,Z which takes BCD number as input');\n", +"disp('so the max value value we can get is 1001');\n", +"disp('By drawing the Karnaugh map(consider all terms above 1001 as dont cares ) the minimised expression is');\n", +"disp('T(w,x,y,z)=wz+xyz^+x^yz');\n", +"disp('T(w,x,y,z)=xyz^+x^yz');\n", +"disp('Draw the series parallel realization of T');\n", +"disp('We can identify the redundancy of y contact at the right end');\n", +"disp('which can be removed');\n", +"disp('The cutset realisation of the above minimized series parallel network is');\n", +"disp('T(w,x,y,z)=(w+y)(x+z)(x^+z^)');" + ] + } +, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 5.5: Minimal_contact_Network.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"clc;\n", +"clear;\n", +"disp('Given minimal contact network is T(w,x,y,z)=wxy+wxz+w^x^y^z^+w^x^yz');\n", +"disp('T(w,x,y,z)=wx(y+z)+w^x^(y^z^+yz)');\n", +"disp('Draw the equivalent series parallel circuit of T');\n", +"disp('Interchange the locations of contacts of w^ and x^ and connect the nodes');\n", +"disp('By connecting in the above manner there is no logical effect since the connection path is not at all used');\n", +"disp('now the lower branch of yz+y^z^ can be written as (y+z^)(y^+z) so transfer contacts can be used');\n", +"disp('This parallel connection enables us to combine two parallel z contacts and thus the minimum spring connection is obtained');" + ] + } +], +"metadata": { + "kernelspec": { + "display_name": "Scilab", + "language": "scilab", + "name": "scilab" + }, + "language_info": { + "file_extension": ".sce", + "help_links": [ + { + "text": "MetaKernel Magics", + "url": "https://github.com/calysto/metakernel/blob/master/metakernel/magics/README.md" + } + ], + "mimetype": "text/x-octave", + "name": "scilab", + "version": "0.7.1" + } + }, + "nbformat": 4, + "nbformat_minor": 0 +} |