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| author | siddhu8990 | 2015-09-15 14:47:02 +0530 |
|---|---|---|
| committer | siddhu8990 | 2015-09-15 14:47:02 +0530 |
| commit | e929ae3e4254caac2d29a832ee75d4ed8ae4a380 (patch) | |
| tree | bc09b45e76c3b62b8249caf8cf7981f38d4da47e /src/c/operations/interfaces/int_OpLogEq.h | |
| parent | fa48de77a489b8b6e7c5cb335b8dc55721cf2a28 (diff) | |
| download | Scilab2C_fossee_old-e929ae3e4254caac2d29a832ee75d4ed8ae4a380.tar.gz Scilab2C_fossee_old-e929ae3e4254caac2d29a832ee75d4ed8ae4a380.tar.bz2 Scilab2C_fossee_old-e929ae3e4254caac2d29a832ee75d4ed8ae4a380.zip | |
Working arduino digital input and output
Diffstat (limited to 'src/c/operations/interfaces/int_OpLogEq.h')
| -rw-r--r-- | src/c/operations/interfaces/int_OpLogEq.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/c/operations/interfaces/int_OpLogEq.h b/src/c/operations/interfaces/int_OpLogEq.h index 446b11c..b693db6 100644 --- a/src/c/operations/interfaces/int_OpLogEq.h +++ b/src/c/operations/interfaces/int_OpLogEq.h @@ -31,6 +31,15 @@ #define c0s0OpLogEqs0(in1,in2) s0c0OpLogEqs0(in2,in1) #define z0d0OpLogEqd0(in1,in2) d0z0OpLogEqd0(in2,in1) +#define u80d0OpLogEqu80(in1,in2) (uint8) (in1 == (uint8)in2) +#define i80d0OpLogEqi80(in1,in2) (int8) (in1 == (int8)in2) +#define u160d0OpLogEqu160(in1,in2) (uint16) (in1 == (uint16)in2) +#define i160d0OpLogEqi160(in1,in2) (int16) (in1 == (int16)in2) + +#define d0u80OpLogEqu80(in1,in2) (uint8) ((uint8)in1 == in2) +#define d0i80OpLogEqi80(in1,in2) (int8) ((int8)in1 == in2) +#define d0u160OpLogEqu160(in1,in2) (uint16) ((uint16)in1 == in2) +#define d0i160OpLogEqi160(in1,in2) (int16) ((int16)in1 == in2) #define s2s0OpLogEqs2(in1,size,in2,out) {int i;\ |