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authorsiddhu89902017-06-21 15:18:15 +0530
committersiddhu89902017-06-21 15:18:15 +0530
commit9abc909f1a02c7c0262e2d53b13504c7ee324fda (patch)
treeba4dfe442b9735204ede017eb0d20f179a5c4b4e /2.3-1/src/c/signalProcessing/interfaces/int_modk.h
parent34bffcd2d147db6733499af5b6f32996d847a733 (diff)
parent5efb98c6773576e39a33df5cfc89979c07031a6a (diff)
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Merged Ukasha's work, code generation for control loop changed
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+/* Copyright (C) 2017 - IIT Bombay - FOSSEE
+
+ This file must be used under the terms of the CeCILL.
+ This source file is licensed as described in the file COPYING, which
+ you should have received as part of this distribution. The terms
+ are also available at
+ http://www.cecill.info/licences/Licence_CeCILL_V2-en.txt
+ Author: Ankit Raj
+ Organization: FOSSEE, IIT Bombay
+ Email: toolbox@scilab.in
+ */
+
+#ifndef __INT_MODK_H__
+#define __INT_MODK_H__
+
+#define d2modkd2(inp,size,oup) dmodka(inp,size[1],oup)
+
+#endif /* !INT_MODK_H__! */