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-rw-r--r--911/CH14/EX14.1.a/ex_14_1_a.pdfbin0 -> 108432 bytes
-rw-r--r--911/CH14/EX14.1.a/ex_14_1_a.sce9
-rw-r--r--911/CH14/EX14.1.b/ex_14_1_b.pdfbin0 -> 108539 bytes
-rw-r--r--911/CH14/EX14.1.b/ex_14_1_b.sce9
-rw-r--r--911/CH14/EX14.1.c/ex_14_1_c.pdfbin0 -> 108437 bytes
-rw-r--r--911/CH14/EX14.1.c/ex_14_1_c.sce9
-rw-r--r--911/CH14/EX14.1.d/ex_14_1_d.pdfbin0 -> 106151 bytes
-rw-r--r--911/CH14/EX14.1.d/ex_14_1_d.sce6
-rw-r--r--911/CH14/EX14.1.e/ex_14_1_e.pdfbin0 -> 106387 bytes
-rw-r--r--911/CH14/EX14.1.e/ex_14_1_e.sce6
-rw-r--r--911/CH14/EX14.2/ex_14_2.pdfbin0 -> 111080 bytes
-rw-r--r--911/CH14/EX14.2/ex_14_2.sce6
-rw-r--r--911/CH14/EX14.3/ex_14_3.pdfbin0 -> 111434 bytes
-rw-r--r--911/CH14/EX14.3/ex_14_3.sce6
-rw-r--r--911/CH14/EX14.4/ex_14_4.pdfbin0 -> 109248 bytes
-rw-r--r--911/CH14/EX14.4/ex_14_4.sce6
-rw-r--r--911/CH14/EX14.5/ex_14_5.pdfbin0 -> 111263 bytes
-rw-r--r--911/CH14/EX14.5/ex_14_5.sce6
18 files changed, 63 insertions, 0 deletions
diff --git a/911/CH14/EX14.1.a/ex_14_1_a.pdf b/911/CH14/EX14.1.a/ex_14_1_a.pdf
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diff --git a/911/CH14/EX14.1.a/ex_14_1_a.sce b/911/CH14/EX14.1.a/ex_14_1_a.sce
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+//example 14.1.a//
+clc
+//clears the screen//
+clear
+//clears all existing variables//
+r=16*1024;
+//given rom capacity//
+row=sqrt(r)
+disp(row,' no of registers in each row = ') \ No newline at end of file
diff --git a/911/CH14/EX14.1.b/ex_14_1_b.pdf b/911/CH14/EX14.1.b/ex_14_1_b.pdf
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diff --git a/911/CH14/EX14.1.b/ex_14_1_b.sce b/911/CH14/EX14.1.b/ex_14_1_b.sce
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@@ -0,0 +1,9 @@
+//example 14.1.b//
+clc
+//clears the screen//
+clear
+//clears all existing variables//
+r=16*1024;
+//given rom capacity//
+column=sqrt(r)
+disp(column,' no of registers in each column = ') \ No newline at end of file
diff --git a/911/CH14/EX14.1.c/ex_14_1_c.pdf b/911/CH14/EX14.1.c/ex_14_1_c.pdf
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diff --git a/911/CH14/EX14.1.c/ex_14_1_c.sce b/911/CH14/EX14.1.c/ex_14_1_c.sce
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index 000000000..f14a24620
--- /dev/null
+++ b/911/CH14/EX14.1.c/ex_14_1_c.sce
@@ -0,0 +1,9 @@
+//example 14.1.c//
+clc
+//clears the screen//
+clear
+//clears all existing variables//
+r=16*1024;
+//given rom capacity//
+c=log2(r)
+disp(c,' total number of address inputs = ') \ No newline at end of file
diff --git a/911/CH14/EX14.1.d/ex_14_1_d.pdf b/911/CH14/EX14.1.d/ex_14_1_d.pdf
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diff --git a/911/CH14/EX14.1.d/ex_14_1_d.sce b/911/CH14/EX14.1.d/ex_14_1_d.sce
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index 000000000..b8fd508a9
--- /dev/null
+++ b/911/CH14/EX14.1.d/ex_14_1_d.sce
@@ -0,0 +1,6 @@
+//example 14.1.d//
+clc
+//clears the screen//
+clear
+//clears all existing variables//
+disp('type of row decoder is 1 to 7 decoder') \ No newline at end of file
diff --git a/911/CH14/EX14.1.e/ex_14_1_e.pdf b/911/CH14/EX14.1.e/ex_14_1_e.pdf
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diff --git a/911/CH14/EX14.1.e/ex_14_1_e.sce b/911/CH14/EX14.1.e/ex_14_1_e.sce
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index 000000000..26acf8f6a
--- /dev/null
+++ b/911/CH14/EX14.1.e/ex_14_1_e.sce
@@ -0,0 +1,6 @@
+//example 14.1.e//
+clc
+//clears the screen//
+clear
+//clears all existing variables//
+disp('type of column decoder is 1 to 7 decoder') \ No newline at end of file
diff --git a/911/CH14/EX14.2/ex_14_2.pdf b/911/CH14/EX14.2/ex_14_2.pdf
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diff --git a/911/CH14/EX14.2/ex_14_2.sce b/911/CH14/EX14.2/ex_14_2.sce
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+//example 14.2//
+clc
+//clears the screen//
+clear
+//clears all existing variables//
+disp('We know that MSB of straight binary number is same as MSB of the Gray code equivalent. This can be passed on as such to the output. In that case, each memory location of the ROM needs to store only a three bit data as the fourth bit is available as such from the input. The required size of ROM is therefore 16*3. The three bit data to be programmed into 16 different memory locations of the ROM corresponding to address inputs of 0000 to 1111 in the same order would be 000, 001, 011, 010, 110, 111, 101, 100, 101, 111, 110, 010, 011, 001, and 000.') \ No newline at end of file
diff --git a/911/CH14/EX14.3/ex_14_3.pdf b/911/CH14/EX14.3/ex_14_3.pdf
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index 000000000..f19ca51a1
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+++ b/911/CH14/EX14.3/ex_14_3.pdf
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diff --git a/911/CH14/EX14.3/ex_14_3.sce b/911/CH14/EX14.3/ex_14_3.sce
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index 000000000..0a96b0177
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+//example 14.3//
+clc
+//clears the screen//
+clear
+//clears all existing variables//
+disp('Since the overall RAM capacity is 32 MB, it will have 25 address inputs(AB0-AB24) as 32M=2^25. For address inputs hex (0000000) to (0FFFFFF), which account for 16M=(2^24) memory locations, RAM-1 is enabled and 16 M locations of RAM 1 are available. RAM-2 is deselected for these address inputs. For address inputs (1000000)hex to (1FFFFFF)hex, the total no of addresses in this group again being equal to 16M, RAM-2 is selected and RAM-1 is deselected. 16M locations of RAM-2 are available. Thus out of 32 MB, 16 MB is stored in RAM-1 and 16 MB is stored in RAM-2.') \ No newline at end of file
diff --git a/911/CH14/EX14.4/ex_14_4.pdf b/911/CH14/EX14.4/ex_14_4.pdf
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index 000000000..e40d9e00c
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diff --git a/911/CH14/EX14.4/ex_14_4.sce b/911/CH14/EX14.4/ex_14_4.sce
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index 000000000..71938ee4a
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+//example 14.4//
+clc
+//clears the screen//
+clear
+//clears all existing variables//
+disp('The address bit AB10 is low for the first 1024 address inputs (from 00000000000 to 01111111111) and ROM - 1 is selected. For the remaining 1024 address inputs (from 10000000000 to 11111111111), AB10 bit is HIGH thus enabling ROM-2.') \ No newline at end of file
diff --git a/911/CH14/EX14.5/ex_14_5.pdf b/911/CH14/EX14.5/ex_14_5.pdf
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diff --git a/911/CH14/EX14.5/ex_14_5.sce b/911/CH14/EX14.5/ex_14_5.sce
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+//example 14.5//
+clc
+//clears the screen//
+clear
+//clears all existing variables//
+disp('For address inputs (00000000)2 to (00001111)2, RAM-1 and RAM-2 are selected. RAM-1 stores higher four bits and RAM-2 stores lower 4 bits of data words corresponding to 16 address inputs mentioned above. This gives us a capacity of 16*8. Now for address inputs (00010000) to (00011111), RAM# and RAM4 are selected. Similarily, RAM3 and RAM 4, respectively store upper and lower four bits of data words corresponding to these address inputs. This again gives a capacity of 16*8. Thus overall capacity is 32*8. The word size is 8. For an address input of 00001101, RAM-1 and RAM-2 will be selected. The address input range for which RAM-1 and RAM-2 are active is (00000000) to (00001111)') \ No newline at end of file
generated by cgit (git 2.34.1) at 2024-12-19 12:58:43 +0000