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diff --git a/3640/CH1/EX1.7/Ex1_7.sce b/3640/CH1/EX1.7/Ex1_7.sce
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+clc
+Vnl=27.3 //no load voltage in volts
+Vfl1=24 //full load voltage at power factor 1 in volts
+mprintf("(Vnl-Vfl/Vfl)=%f\n",(Vnl-Vfl1)/Vfl1) //ans may vary due to roundoff error
+Vfl2=22.1 //full load voltage at power factor 0.7 in volts
+mprintf("Voltage Regulation=%f",(Vnl-Vfl2)/Vfl1)
+
+
+
+