2 files changed, 21 insertions, 0 deletions
diff --git a/275/CH3/EX3.3.58/Ch3_3_58.sce b/275/CH3/EX3.3.58/Ch3_3_58.sce
new file mode 100755
index 000000000..a60716fc7
--- /dev/null
+++ b/275/CH3/EX3.3.58/Ch3_3_58.sce
@@ -0,0 +1,21 @@
+clc
+disp("Example 3.58")
+printf("\n")
+disp("Draw the DC load line & determine Rc for base bias circuit")
+printf("Given\n")
+//given
+Vcc=18
+Vbe=0.7
+Vceq=9
+Icq=2*10^-3
+//to find Rc
+Rc=(Vcc-Vceq)/Icq //from circuit
+//to draw DC load line
+Ic1=Vcc/Rc
+Vce=[Vcc Vceq 0]
+Ic=[0 Icq Ic1]
+printf("Q(%f volt,%f ampere)\n",Vceq,Icq)
+plot2d(Vce, Ic)
+xlabel("Vce in volt")
+ylabel("Ic in ampere")
+xtitle("DC load line for base bias circuit")
diff --git a/275/CH3/EX3.3.58/Ch3_58.png b/275/CH3/EX3.3.58/Ch3_58.png
new file mode 100755
index 000000000..3f0d971e7
--- /dev/null
+++ b/275/CH3/EX3.3.58/Ch3_58.png