1 files changed, 27 insertions, 0 deletions
diff --git a/275/CH3/EX3.3.50/Ch3_3_50.sce b/275/CH3/EX3.3.50/Ch3_3_50.sce
new file mode 100755
index 000000000..09acb98e5
--- /dev/null
+++ b/275/CH3/EX3.3.50/Ch3_3_50.sce
@@ -0,0 +1,27 @@
+clc
+disp("Example 3.50")
+printf("\n")
+disp("Draw a DC load line for the base bias circuit")
+printf("Given\n")
+//given
+Rc=2.2*10^3
+Rb=470*10^3
+Vcc=18
+Vbe=0.7
+hFE=100
+//find the Ib
+Ib=(Vcc-Vbe)/Rb  // from ciruit
+//find the Ic
+Icq=hFE*Ib
+//find the Vceq
+Vceq=Vcc-(Icq*Rc)
+//to draw Dc load line 
+Ic1=Vcc/Rc
+Vce1=Vcc
+Vce=[Vcc Vceq 0]
+Ic=[0 Icq Ic1]
+printf("Q(%f,%f)\n",Vceq,Icq)
+plot2d(Vce, Ic)
+xlabel("Vce in volt")
+ylabel("Ic in Ampere")
+xtitle("DC load line for base bias circuit")