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| author | prashantsinalkar | 2017-10-10 12:27:19 +0530 |
|---|---|---|
| committer | prashantsinalkar | 2017-10-10 12:27:19 +0530 |
| commit | 7f60ea012dd2524dae921a2a35adbf7ef21f2bb6 (patch) | |
| tree | dbb9e3ddb5fc829e7c5c7e6be99b2c4ba356132c /911/CH9/EX9.10.a/ex_9_10_a.sce | |
| parent | b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b (diff) | |
| download | Scilab-TBC-Uploads-7f60ea012dd2524dae921a2a35adbf7ef21f2bb6.tar.gz Scilab-TBC-Uploads-7f60ea012dd2524dae921a2a35adbf7ef21f2bb6.tar.bz2 Scilab-TBC-Uploads-7f60ea012dd2524dae921a2a35adbf7ef21f2bb6.zip | |
initial commit / add all books
Diffstat (limited to '911/CH9/EX9.10.a/ex_9_10_a.sce')
| -rw-r--r-- | 911/CH9/EX9.10.a/ex_9_10_a.sce | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/911/CH9/EX9.10.a/ex_9_10_a.sce b/911/CH9/EX9.10.a/ex_9_10_a.sce new file mode 100644 index 000000000..148b3cbd0 --- /dev/null +++ b/911/CH9/EX9.10.a/ex_9_10_a.sce @@ -0,0 +1,6 @@ +//example 9.10(a)//
+clc
+//clears the screen//
+clear
+//clears all existing variables//
+disp('At the end of eigth LOW to HIGH clock transition, the data bits loaded into the register will be 10110010, with ''0'' on the extreme right appearing at the Q7 output. The ninth clock transition will shift this 0 out of the register and the next adjacent bit (i.e.''1'') will take its place on Q7 output. Each subsequent clock pulse will shift the bits one step towards right with the result that at the end of 11th clock transition, the Q7 output will be logic ''0''. ')
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