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authorprashantsinalkar2017-10-10 12:27:19 +0530
committerprashantsinalkar2017-10-10 12:27:19 +0530
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+//example 3.6//
+//how to convert exor gate to not//
+clc
+//clears all variables//
+clear
+//clears the screen//
+disp('here if we look at truth table of ex-or gate we notice that if one of its input is tied to logic 1 then the reult is that of a not gate') \ No newline at end of file