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| author | prashantsinalkar | 2017-10-10 12:27:19 +0530 |
|---|---|---|
| committer | prashantsinalkar | 2017-10-10 12:27:19 +0530 |
| commit | 7f60ea012dd2524dae921a2a35adbf7ef21f2bb6 (patch) | |
| tree | dbb9e3ddb5fc829e7c5c7e6be99b2c4ba356132c /911/CH3/EX3.13/ex_3_13.sce | |
| parent | b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b (diff) | |
| download | Scilab-TBC-Uploads-7f60ea012dd2524dae921a2a35adbf7ef21f2bb6.tar.gz Scilab-TBC-Uploads-7f60ea012dd2524dae921a2a35adbf7ef21f2bb6.tar.bz2 Scilab-TBC-Uploads-7f60ea012dd2524dae921a2a35adbf7ef21f2bb6.zip | |
initial commit / add all books
Diffstat (limited to '911/CH3/EX3.13/ex_3_13.sce')
| -rw-r--r-- | 911/CH3/EX3.13/ex_3_13.sce | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/911/CH3/EX3.13/ex_3_13.sce b/911/CH3/EX3.13/ex_3_13.sce new file mode 100644 index 000000000..885332378 --- /dev/null +++ b/911/CH3/EX3.13/ex_3_13.sce @@ -0,0 +1,6 @@ +//example 3.13//
+clc
+//clears the screen//
+clear
+//clears all existing variables//
+disp('The NAND gates are used in the circuit are open collector gates. Paralleling of the two NAND gates at the input leads to a WIRE AND connection. Therefore the logic expression at the point where the two outputs combine is given by the equation (AB)''.(CD)''. Using Demorgan''s theorem (AB)''.(CD)''=(AB+CD)''. The third NAND is wired as an inverter. Therefore the final output can be written as : Y = AB + CD')
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