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| author | priyanka | 2015-06-24 15:03:17 +0530 |
|---|---|---|
| committer | priyanka | 2015-06-24 15:03:17 +0530 |
| commit | b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b (patch) | |
| tree | ab291cffc65280e58ac82470ba63fbcca7805165 /876/CH6/EX6.2 | |
| download | Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.tar.gz Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.tar.bz2 Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.zip | |
initial commit / add all books
Diffstat (limited to '876/CH6/EX6.2')
| -rwxr-xr-x | 876/CH6/EX6.2/Ex6_2.sce | 13 | ||||
| -rwxr-xr-x | 876/CH6/EX6.2/Ex6_2.txt | 3 | ||||
| -rwxr-xr-x | 876/CH6/EX6.2/Ex6_2t.txt | 13 |
3 files changed, 29 insertions, 0 deletions
diff --git a/876/CH6/EX6.2/Ex6_2.sce b/876/CH6/EX6.2/Ex6_2.sce new file mode 100755 index 000000000..456efe295 --- /dev/null +++ b/876/CH6/EX6.2/Ex6_2.sce @@ -0,0 +1,13 @@ +//caption:Find output voltage
+//Ex6.2
+clc
+clear
+close
+Lo=0//input voltage logic0(in V)
+L1=20//input voltage logic1(in V)
+V1msb=L1/2
+V2msb=L1/4
+V3msb=L1/8
+V4msb=L1/16
+Va=V1msb+V2msb+V3msb+V4msb
+disp(Va,'output voltage(in V)=')
\ No newline at end of file diff --git a/876/CH6/EX6.2/Ex6_2.txt b/876/CH6/EX6.2/Ex6_2.txt new file mode 100755 index 000000000..39be2c164 --- /dev/null +++ b/876/CH6/EX6.2/Ex6_2.txt @@ -0,0 +1,3 @@ +output voltage(in V)=
+
+ 18.75
\ No newline at end of file diff --git a/876/CH6/EX6.2/Ex6_2t.txt b/876/CH6/EX6.2/Ex6_2t.txt new file mode 100755 index 000000000..456efe295 --- /dev/null +++ b/876/CH6/EX6.2/Ex6_2t.txt @@ -0,0 +1,13 @@ +//caption:Find output voltage
+//Ex6.2
+clc
+clear
+close
+Lo=0//input voltage logic0(in V)
+L1=20//input voltage logic1(in V)
+V1msb=L1/2
+V2msb=L1/4
+V3msb=L1/8
+V4msb=L1/16
+Va=V1msb+V2msb+V3msb+V4msb
+disp(Va,'output voltage(in V)=')
\ No newline at end of file |