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| author | prashantsinalkar | 2017-10-10 12:27:19 +0530 |
|---|---|---|
| committer | prashantsinalkar | 2017-10-10 12:27:19 +0530 |
| commit | 7f60ea012dd2524dae921a2a35adbf7ef21f2bb6 (patch) | |
| tree | dbb9e3ddb5fc829e7c5c7e6be99b2c4ba356132c /863/CH11/EX11.3/Ex11_3.txt | |
| parent | b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b (diff) | |
| download | Scilab-TBC-Uploads-7f60ea012dd2524dae921a2a35adbf7ef21f2bb6.tar.gz Scilab-TBC-Uploads-7f60ea012dd2524dae921a2a35adbf7ef21f2bb6.tar.bz2 Scilab-TBC-Uploads-7f60ea012dd2524dae921a2a35adbf7ef21f2bb6.zip | |
initial commit / add all books
Diffstat (limited to '863/CH11/EX11.3/Ex11_3.txt')
| -rw-r--r-- | 863/CH11/EX11.3/Ex11_3.txt | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/863/CH11/EX11.3/Ex11_3.txt b/863/CH11/EX11.3/Ex11_3.txt new file mode 100644 index 000000000..53cd5c6f5 --- /dev/null +++ b/863/CH11/EX11.3/Ex11_3.txt @@ -0,0 +1,14 @@ +//Caption:Determine output for given logic circuit
+//Ex11.3
+clc;
+clear;
+close;
+A=1
+B=0
+C=1
+D=1
+c=A-1
+n=c//Output of NOT gate
+a=B*C*D//Output of AND gate
+o=c+(B*C*D)//Output of OR gate
+disp(o,'Output for given logic circuit is=')
\ No newline at end of file |