initial commit / add all books

11 files changed, 155 insertions, 0 deletions

diff --git a/74/CH10/EX10.1/example1_sce.sce b/74/CH10/EX10.1/example1_sce.sce
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+//chapter 10

+//example 10.1

+//page 345

+Vnl=12;

+Vfl=11.6;

+Ilmax=100*10^-3;

+LR=Vnl-Vfl;//load regulation

+disp(LR)

+percentage=((Vnl-Vfl)/Vfl)*100//% LOAD REGULATION

+Vout=LR;

+Ro=Vout/Ilmax;//output resistance

+disp(Ro)
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diff --git a/74/CH10/EX10.10/example10_sce.sce b/74/CH10/EX10.10/example10_sce.sce
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+//chapter 10

+//example 10.10

+//page 357

+Vref=-1.25;

+Iadj=50*10^-6;

+R1=240;

+R2min=0;//to find minimum output voltage correspond to R2min=0

+Voutmin=Vref*(1+(R2min/R1))+Iadj*R2min;

+disp(Voutmin)

+R2max=5*10^3;//for maximum output voltage 

+Voutmax=Vref*(1+(R2max/R1))+Iadj*R2max;

+disp(Voutmax)//volts
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diff --git a/74/CH10/EX10.11/example11_sce.sce b/74/CH10/EX10.11/example11_sce.sce
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index 000000000..e4eb95529
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+++ b/74/CH10/EX10.11/example11_sce.sce
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+//chapter10

+//example 10.11

+//page 10.11

+Vo=5;Io=50*10^-3;

+Isc=75*10^-3;Vin=15;

+Vsense=.6;Vref=7;

+I=1*10^-3;//current through R1 and R2

+R2=Vo/I;

+disp(R2)

+VR1=Vref-Vo;//voltage across R1

+disp(VR1)

+R1=VR1/I;

+disp(R1)

+R3=R1*R2/(R1+R2);//R3=R1||R2

+disp(R3)

+Rsc=Vsense/Isc;

+disp(Rsc)

+C1=7.4*10^-6/10;

+disp(R1,R2,R3,Rsc,C1)//component value
\ No newline at end of file
diff --git a/74/CH10/EX10.12/example12_sce.sce b/74/CH10/EX10.12/example12_sce.sce
new file mode 100755
index 000000000..f37940622
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+++ b/74/CH10/EX10.12/example12_sce.sce
@@ -0,0 +1,21 @@
+//chapter 10

+//example 10.12

+//page 372

+Vref=7;Vout=5;Vin=15;

+Il=1*10^-3;Isc=1.5;Vsense=.65;

+Imax=150*10^-3;//Imax of IC-723 is 150mA

+R1=(Vref-Vout)/Il;

+disp(R1)

+R2=Vout/Il;

+disp(R2)

+R3=(R1*R2)/(R1+R2);

+disp(R3)

+Rsc=Vsense/Isc;

+disp(Rsc)

+Bmin=Il/Imax

+Pd=(Vin-Vout)*Isc

+Icmax=2*Isc;//Maximum collector current

+disp(Icmax)

+Vout=0;//maximum collector to emitter voltage can be calculated as under the voltage across Q will maximum when the load is short circuited

+Vcemax=Vin-Vout;

+disp(Vcemax)
\ No newline at end of file
diff --git a/74/CH10/EX10.13/example13_sce.sce b/74/CH10/EX10.13/example13_sce.sce
new file mode 100755
index 000000000..8df9708fc
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+++ b/74/CH10/EX10.13/example13_sce.sce
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+//chapter 10

+//example 10.13

+//page 373

+Vref=7;Vsense=.65;

+Voutmin=9;Voutmax=12; I1=.5;Imax=150*10^-3;

+R2=10*10^3;//let assume

+//(R1+R2)/R2=Vout/Vref-----------eq(1)

+R1min=2*R2/7;

+disp(R1min)

+Voutmax=12

+R1max=5*R2/7;//using eq (1)

+disp(R1max)

+Rsc=Vsense/Il;

+disp(Rsc)

+R3=(R1max*R2)/(R1max+R2)

+Bmin=Il/Imax;

+disp(Bmin)
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diff --git a/74/CH10/EX10.14/example14_sce.sce b/74/CH10/EX10.14/example14_sce.sce
new file mode 100755
index 000000000..dcb0c8f58
--- /dev/null
+++ b/74/CH10/EX10.14/example14_sce.sce
@@ -0,0 +1,15 @@
+//chapter 10

+//example 10.14

+//page 376

+Rl=10;Iq=4.3*10^-3;

+Vr=5;Il=.5;

+// Il=Vr/R+Iq

+R=Vr/(Il-Iq);

+disp(R)

+power=(Il^2)*R;//wattage of reisstor

+disp(power)

+Vout=Vr+Il*R;//output voltage with respect to ground

+disp(Vout)

+Vd=2;//minimum voltage drop across IC 7805 which is called as drop out voltage is 2V

+Vin=Vout+Vd;

+disp(Vin)
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diff --git a/74/CH10/EX10.2/example2_sce.sce b/74/CH10/EX10.2/example2_sce.sce
new file mode 100755
index 000000000..76e3cb62c
--- /dev/null
+++ b/74/CH10/EX10.2/example2_sce.sce
@@ -0,0 +1,10 @@
+//chapter10

+//example 10.2

+//page347

+RF=.1;//ripple factor

+Vldc=10;

+//ripple factor=Vrms/Vldc

+Vrms=Vldc*RF;

+disp(Vrms)

+Vp_p=2*sqrt(2)*Vrms;//peak to peak ripple

+disp(Vp_p)//volts
\ No newline at end of file
diff --git a/74/CH10/EX10.3/example3_sce.sce b/74/CH10/EX10.3/example3_sce.sce
new file mode 100755
index 000000000..9ccd9bb5f
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+//chapter 10

+//example 10.3

+//page349

+V_=6;Vz=6;//potential at inverting(-) input is equal to vitual

+Vr2=Vz;

+Vin=30;

+Rl=200;

+R2=5*10^3;

+R1=0;//for minimum Vout

+Voutmin=((R1+R2)/R2)*Vz;//minimum output voltage

+disp(Voutmin)//minimum voltage

+R1=10*10^3;//for maximum output voltage

+Voutmax=((R1+R2)/R2)*Vz;

+disp(Voutmax)//maximum output voltage

+disp(Voutmax,Voutmin)//range when potentiometer change from 0 to 10k

+Vce=Vin-Voutmax;//when R1=10k and Vout=18

+disp(Vce)

+Ic=Voutmax/Rl;

+disp(Ic)

+Pd=Vce*Ic;//power

+disp(Pd)//watt
\ No newline at end of file
diff --git a/74/CH10/EX10.4/example4_sce.sce b/74/CH10/EX10.4/example4_sce.sce
new file mode 100755
index 000000000..792e37ec3
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+++ b/74/CH10/EX10.4/example4_sce.sce
@@ -0,0 +1,9 @@
+//chapter 10

+//example 10.4

+//page 350 figure 10.9

+Vz=5;

+V_=5;

+R2=15;R3=15;

+//V_ across R3

+Vout=((R2+R3)/R3)*(V_)//voltage across R3

+disp(Vout)
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diff --git a/74/CH10/EX10.5/example5_sce.sce b/74/CH10/EX10.5/example5_sce.sce
new file mode 100755
index 000000000..433ba5024
--- /dev/null
+++ b/74/CH10/EX10.5/example5_sce.sce
@@ -0,0 +1,10 @@
+//chapter 10

+// example 10.5

+// page 351

+R1=20

+Vin=12;

+Vout=0;//worst case  for masimum power across R1

+VR1=Vin-Vout;

+disp(VR1)

+PR1=VR1^2/R1;

+disp(PR1)//watt
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diff --git a/74/CH10/EX10.6/example6_sce.sce b/74/CH10/EX10.6/example6_sce.sce
new file mode 100755
index 000000000..d3009de5d
--- /dev/null
+++ b/74/CH10/EX10.6/example6_sce.sce
@@ -0,0 +1,9 @@
+//chapter 10

+//eaxmple 10.6

+//page 354

+Iq=4.3*10^-3;

+R2=100;

+Vout=7;//for maximum output voltage

+Vr=5;//for R2 is maximum

+//Vout=Vout(1+R2/R1)+Iq*R2

+R1=100/(((Vout-Iq*R2)/Vr)-1)
\ No newline at end of file