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| author | priyanka | 2015-06-24 15:03:17 +0530 |
|---|---|---|
| committer | priyanka | 2015-06-24 15:03:17 +0530 |
| commit | b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b (patch) | |
| tree | ab291cffc65280e58ac82470ba63fbcca7805165 /506/CH6/EX6.5.b | |
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initial commit / add all books
Diffstat (limited to '506/CH6/EX6.5.b')
| -rwxr-xr-x | 506/CH6/EX6.5.b/Example6_5b.sce | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/506/CH6/EX6.5.b/Example6_5b.sce b/506/CH6/EX6.5.b/Example6_5b.sce new file mode 100755 index 000000000..f22589cb9 --- /dev/null +++ b/506/CH6/EX6.5.b/Example6_5b.sce @@ -0,0 +1,31 @@ +clear;
+clc;
+
+//Caption:When atleast one input is at V(0) in NAND gate
+//Given Data
+//For transistor
+Vbesat=0.8;//in V
+Vy=0.5;//in V
+Vcesat=0.2;//in V
+R = 5;//in K
+Rc = 2.2;//in K
+
+//For diode
+Vyd=0.6;//Vgamma in V
+Vdrop=0.7;//in V
+
+//The logic levels are Vcesato=0.2V for 0 state
+Vcesato=0.2;//in V
+
+disp('If atleast one input is in 0 state');
+Vp = Vcesato + Vdrop;//Voltage at point P
+disp('V',Vp,'Vp=');
+Vbe = Vp-Vyd;//Voltage at base emitter
+disp('V',Vbe,'Vbe=');
+if(Vbe<Vy)
+ disp('Q is cutoff');
+end
+if(Vbe>Vy)
+ disp('Q is ON');
+end
+//end
\ No newline at end of file |