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| author | priyanka | 2015-06-24 15:03:17 +0530 |
|---|---|---|
| committer | priyanka | 2015-06-24 15:03:17 +0530 |
| commit | b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b (patch) | |
| tree | ab291cffc65280e58ac82470ba63fbcca7805165 /462/CH12/EX12.1/ex_12_1.sce | |
| download | Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.tar.gz Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.tar.bz2 Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.zip | |
initial commit / add all books
Diffstat (limited to '462/CH12/EX12.1/ex_12_1.sce')
| -rwxr-xr-x | 462/CH12/EX12.1/ex_12_1.sce | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/462/CH12/EX12.1/ex_12_1.sce b/462/CH12/EX12.1/ex_12_1.sce new file mode 100755 index 000000000..ed1cedef5 --- /dev/null +++ b/462/CH12/EX12.1/ex_12_1.sce @@ -0,0 +1,8 @@ +//example 12.1//
+//find the product term//
+clc
+//clears the screen//
+clear
+//clears already existing variables//
+disp('For an open link, the input to AND gate is logic 1, whereas for a closed link the corresponding input to the AND gate is same as the voltage applied at that input, therefore,')
+disp('P(o)=I(o)I(2)''I(3)''I(6)')
\ No newline at end of file |