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author | prashantsinalkar | 2017-10-10 12:27:19 +0530 |
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committer | prashantsinalkar | 2017-10-10 12:27:19 +0530 |
commit | 7f60ea012dd2524dae921a2a35adbf7ef21f2bb6 (patch) | |
tree | dbb9e3ddb5fc829e7c5c7e6be99b2c4ba356132c /3809/CH17/EX17.6/EX17_6.sce | |
parent | b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b (diff) | |
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diff --git a/3809/CH17/EX17.6/EX17_6.sce b/3809/CH17/EX17.6/EX17_6.sce new file mode 100644 index 000000000..d362fee18 --- /dev/null +++ b/3809/CH17/EX17.6/EX17_6.sce @@ -0,0 +1,21 @@ +//Chapter 17, Example 17.6 +clc +//Initialisation +rd=50*100*3 //resistance in ohm +gm=72*10**-3 //in siemens +Rd=3.3*10**3 //resistance in ohm +Rs=10**3 //resistance in ohm + + + +//Calculation +av=-Rd/Rs //votlage gain from eq 17.7 +b=gm*Rd +c=gm*Rs +av1=-(b)/(1+(c)+((Rd+Rs)/rd)) //voltage gain from eq 17.8 +av2=-(b)/(1+(c)) //voltage gain from eq 17.9 + +//Results +printf("From Eq 17.7, Gain = %.1f\n",av) +printf("From Eq 17.8, Gain = %.3f\n",av1) +printf("From Eq 17.9, Gain = %.3f\n",av2) |