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| author | prashantsinalkar | 2017-10-10 12:27:19 +0530 |
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| committer | prashantsinalkar | 2017-10-10 12:27:19 +0530 |
| commit | 7f60ea012dd2524dae921a2a35adbf7ef21f2bb6 (patch) | |
| tree | dbb9e3ddb5fc829e7c5c7e6be99b2c4ba356132c /3745/CH1/EX1.59 | |
| parent | b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b (diff) | |
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initial commit / add all books
Diffstat (limited to '3745/CH1/EX1.59')
| -rw-r--r-- | 3745/CH1/EX1.59/Ex1_59.sce | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/3745/CH1/EX1.59/Ex1_59.sce b/3745/CH1/EX1.59/Ex1_59.sce new file mode 100644 index 000000000..f7786bd9f --- /dev/null +++ b/3745/CH1/EX1.59/Ex1_59.sce @@ -0,0 +1,18 @@ +// Ex 59 Page 402 + +clc;clear;close; +// Given +u=45;//degree +m=3;//no of phases + +//Id=sqrt(2)*Vs*X*(1-cosd(u))*sin(%pi/m) +IdBYVs_dash=m/2/%pi*(1-cosd(u))*sin(%pi/m)*sqrt(2);//load current/Vs +//where IdBYVs_dash = m/%pi*IdX/2 +EdoBYVs=sqrt(2)*m/%pi*sin(%pi/m);//dc output voltage/Vs with no overlap +EduBYVs=EdoBYVs-IdBYVs_dash;//dc output voltage/Vs with overlap +//part (a) +Reg1=(EdoBYVs-EduBYVs)/EdoBYVs*100;//% (regulation) +printf("part(a) Regulation at no load voltage = %.f percent",Reg1) +//part (b) +Reg2=(EdoBYVs-EduBYVs)/EduBYVs*100;//% (regulation) +printf("\n part(b) Regulation at full load voltage = %.f percent",Reg2) |