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| author | priyanka | 2015-06-24 15:03:17 +0530 |
|---|---|---|
| committer | priyanka | 2015-06-24 15:03:17 +0530 |
| commit | b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b (patch) | |
| tree | ab291cffc65280e58ac82470ba63fbcca7805165 /275/CH3/EX3.3.74 | |
| download | Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.tar.gz Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.tar.bz2 Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.zip | |
initial commit / add all books
Diffstat (limited to '275/CH3/EX3.3.74')
| -rwxr-xr-x | 275/CH3/EX3.3.74/Ch3_3_74.sce | 38 | ||||
| -rwxr-xr-x | 275/CH3/EX3.3.74/Ch3_74.png | bin | 0 -> 3405 bytes |
2 files changed, 38 insertions, 0 deletions
diff --git a/275/CH3/EX3.3.74/Ch3_3_74.sce b/275/CH3/EX3.3.74/Ch3_3_74.sce new file mode 100755 index 000000000..a34f72ed9 --- /dev/null +++ b/275/CH3/EX3.3.74/Ch3_3_74.sce @@ -0,0 +1,38 @@ +clc
+disp("Example 3.74")
+printf("\n")
+disp("Find the Ve, Ic,Vce & Vc. Draw a DC load line for Voltage divider circuit")
+printf("Given\n")
+//given
+Vcc=15
+Vbe=0.7
+hFE=50
+R1=6.8*10^3
+R2=3.3*10^3
+Rc=0.9*10^3
+Re=0.9*10^3
+//thevenin voltage
+Vt=(Vcc*R2)/(R1+R2)
+//thevenin resistance
+Rt=(R1*R2)/(R1+R2)
+//base current
+Ib=(Vt-Vbe)/(Rt+(1+hFE)*Re)
+//collector current
+Icq=hFE*Ib
+//emitter current
+Ie=Ib+Icq
+//emitter voltage
+Ve=Ie*Re
+//collector to emitter voltage
+Vceq=Vcc-(Icq*Rc)-(Ie*Re)
+//collector voltage
+Vc=Vce+Ve
+//to draw DC load line
+Ic1=Vcc/(Rc+Re)
+Vce=[Vcc Vceq 0]
+Ic=[0 Icq Ic1]
+printf("Q(%f,%f)\n",Vceq,Icq)
+plot2d(Vce, Ic)
+xlabel("Vce")
+ylabel("Ic")
+xtitle("DC load line for base bias circuit")
\ No newline at end of file diff --git a/275/CH3/EX3.3.74/Ch3_74.png b/275/CH3/EX3.3.74/Ch3_74.png Binary files differnew file mode 100755 index 000000000..d5906b298 --- /dev/null +++ b/275/CH3/EX3.3.74/Ch3_74.png |
