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author | priyanka | 2015-06-24 15:03:17 +0530 |
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committer | priyanka | 2015-06-24 15:03:17 +0530 |
commit | b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b (patch) | |
tree | ab291cffc65280e58ac82470ba63fbcca7805165 /2522/CH3/EX3.5 | |
download | Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.tar.gz Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.tar.bz2 Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.zip |
initial commit / add all books
Diffstat (limited to '2522/CH3/EX3.5')
-rwxr-xr-x | 2522/CH3/EX3.5/exm3_5.sce | 17 | ||||
-rwxr-xr-x | 2522/CH3/EX3.5/exm3_5_output.jpg | bin | 0 -> 51636 bytes |
2 files changed, 17 insertions, 0 deletions
diff --git a/2522/CH3/EX3.5/exm3_5.sce b/2522/CH3/EX3.5/exm3_5.sce new file mode 100755 index 000000000..1dc756e20 --- /dev/null +++ b/2522/CH3/EX3.5/exm3_5.sce @@ -0,0 +1,17 @@ +////page no 91
+//example no 3.5
+//MEMORY ADDRESS RANGE OF 6116.
+clc;
+printf('A10-A0 are address lines for register select. \n');
+printf('A15-A11 are address lines for chip select. \n \n');
+printf('A15 A14 A13 A12 A11 \n');
+printf(' 1 0 0 0 1 \n \n'); //chip select bits have to be active low always to select that chip.
+printf('A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 \n');
+printf('0 0 0 0 0 0 0 0 0 0 0 \n'); //this selects the register
+printf('The above combination selects the memory address 8800H. \n \n');
+printf('A15 A14 A13 A12 A11 \n');
+printf(' 1 0 0 0 1 \n \n'); //chip select bits have to be active low always to select that chip.
+printf('A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 \n');
+printf('1 1 1 1 1 1 1 1 1 1 1 \n'); //this selects the register
+printf('The above combination selects the memory address 88FFH. \n \n');
+//thus this chip can select any memory location from 8800H to 88FFH.
diff --git a/2522/CH3/EX3.5/exm3_5_output.jpg b/2522/CH3/EX3.5/exm3_5_output.jpg Binary files differnew file mode 100755 index 000000000..db6f257b4 --- /dev/null +++ b/2522/CH3/EX3.5/exm3_5_output.jpg |