initial commit / add all books

6 files changed, 94 insertions, 0 deletions

diff --git a/2300/CH19/EX19.29.1/Ex19_1.sce b/2300/CH19/EX19.29.1/Ex19_1.sce
new file mode 100755
index 000000000..94334c3f1
--- /dev/null
+++ b/2300/CH19/EX19.29.1/Ex19_1.sce
@@ -0,0 +1,18 @@
+//scilab 5.4.1

+//Windows 7 operating system

+//chapter 19 VLSI Technology and Circuits

+clc

+clear

+ID=50*10^-6//ID=drain current in amperes

+k=25*10^-6//k=ue/D in A/V^2

+VDS=0.25//VDS=drain-to-source voltage

+VGS=5//VGS=gate-to-source voltage

+VTH=1.5//VTH=threshold voltage

+w=ID/(k*(VGS-VTH)*VDS)//w=W/L

+format("v",5)

+disp(w,"W/L=")

+P=VDS*ID//P=power dissipated by the transistor

+disp("micro Watt",P*10^6,"The dissipated power is=")

+VDD=5//VDD=drain supply voltage of given NMOS transistor

+R=(VDD-VDS)/ID//R=load resistor to be connected in series with the drain

+disp("kilo ohm",R/1000,"The load resistance is=")

diff --git a/2300/CH19/EX19.29.2/Ex19_2.sce b/2300/CH19/EX19.29.2/Ex19_2.sce
new file mode 100755
index 000000000..2894fae55
--- /dev/null
+++ b/2300/CH19/EX19.29.2/Ex19_2.sce
@@ -0,0 +1,17 @@
+//scilab 5.4.1

+//Windows 7 operating system

+//chapter 19 VLSI Technology and Circuits

+clc

+clear

+ID=50*10^-6//ID=drain current in amperes

+k=25*10^-6//k=ue/D in A/V^2

+VDEP=3

+l=(k*((-VDEP)^2))/(2*ID)//l=(L/W)=aspect ratio of the pull-up

+disp(l,"Pull-up (L/W)=")

+VGS=5//VGS=gate-to-source voltage

+VTH=1//VTH=threshold voltage

+VDs=4.75//VDs=the drain source voltage of the depletion mode pull-up in saturation

+VDD=5//VDD=drain supply voltage of given NMOS inverter

+//L/W=(k*(VGS-VTH)*VDS)/ID where L/W=pull down aspect ratio

+l1=(k*(VGS-VTH)*(VDD-VDs))/ID//l1=L/W

+disp(l1,"Pull-down (L/W)=")

diff --git a/2300/CH19/EX19.29.3/Ex19_3.sce b/2300/CH19/EX19.29.3/Ex19_3.sce
new file mode 100755
index 000000000..d1c44ee41
--- /dev/null
+++ b/2300/CH19/EX19.29.3/Ex19_3.sce
@@ -0,0 +1,14 @@
+//scilab 5.4.1

+//Windows 7 operating system

+//chapter 19 VLSI Technology and Circuits

+clc

+clear

+w=10//w=W/L value of the NMOS transistor in a CMOS inverter

+un=1350//un=electron mobility for NMOS transistor in cm^2/V s

+up=540//up=electron mobility for PMOS transistor in cm^2/V s

+//(Wpu/Lpu)*up*(VINV-VDD-VTHP)^2=(Wpd/Lpd)*un*(VINV-VTHN)^2

+//For a symmetrical inverter VINV=(VDD/2) and VTHN=(-VTHP)

+//Also for input voltage=VDD/2 both transistors operate in saturation region

+//Therefore,up*(Wpu/Lpu)=un*(Wpd/Lpd)

+w1=(un*w)/up//w1=Wpu/Lpu=W/L value of the PMOS for a symmetrical inverter

+disp(w1,"W/L value of the PMOS transistor in a CMOS inverter is =")

diff --git a/2300/CH19/EX19.29.4/Ex19_4.sce b/2300/CH19/EX19.29.4/Ex19_4.sce
new file mode 100755
index 000000000..6e65a9380
--- /dev/null
+++ b/2300/CH19/EX19.29.4/Ex19_4.sce
@@ -0,0 +1,13 @@
+//scilab 5.4.1

+//Windows 7 operating system

+//chapter 19 VLSI Technology and Circuits

+clc

+clear

+f=2*10^9//f=clock frequency in Hz

+VDD=3//VDD=drain supply voltage 

+Cl=1*10^-12//C1=load capacitance in Farad

+P=50*10^-3//P=maximum power dissipation capability in W/stage

+N=P/(f*Cl*VDD^2)//N=maximum permissible number of fan outs

+format("v",5)

+disp(N,"N=")

+disp(floor(N),"The maximum permissible number of fan-outs is(integer just below actual value)=")

diff --git a/2300/CH19/EX19.29.5/Ex19_5.sce b/2300/CH19/EX19.29.5/Ex19_5.sce
new file mode 100755
index 000000000..fff6682b4
--- /dev/null
+++ b/2300/CH19/EX19.29.5/Ex19_5.sce
@@ -0,0 +1,11 @@
+//scilab 5.4.1

+//Windows 7 operating system

+//chapter 19 VLSI Technology and Circuits

+clc

+clear

+L=3*10^-6//L=length of an NMOS pass transistor in metres

+VDS=0.5//VDS=drain-source voltage

+u=1400*10^-4//u=electron mobility in m^2/V s

+t=L^2/(VDS*u)//t=channel transit time

+format("v",5)

+disp("nanoseconds",t/10^-9,"The transit time is=")

diff --git a/2300/CH19/EX19.29.6/Ex19_6.sce b/2300/CH19/EX19.29.6/Ex19_6.sce
new file mode 100755
index 000000000..ecec44b07
--- /dev/null
+++ b/2300/CH19/EX19.29.6/Ex19_6.sce
@@ -0,0 +1,21 @@
+//scilab 5.4.1

+//Windows 7 operating system

+//chapter 19 VLSI Technology and Circuits

+clc

+clear

+y=2//y=length unit in micrometres

+W=3*y//W=mimimum metal linewidth in micrometres

+disp("micrometres",W,"W=")

+n=80//n=number of driven inverters

+i=0.07//i=average current ratings in milliamperes

+I=n*i//I=total currrent drawn by n inverters

+disp("mA",I,"I=")

+//1mA per micrometre of aluminium line width is the maximum safe average current an aluminium wire can carry.

+disp("This needs a line at least width of")

+disp("micrometres",I)

+if (W>I) then

+    disp("Above calculated minimum metal line-width (W) is thus the safe width of the metal line driving 80 inverters.")

+end

+f=5//f=number of fanout lines

+w=f*W//w=required metal line width

+disp("micrometres",w,"The metal line-width required to supply a fan-out of 5 lines is=")