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| author | priyanka | 2015-06-24 15:03:17 +0530 |
|---|---|---|
| committer | priyanka | 2015-06-24 15:03:17 +0530 |
| commit | b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b (patch) | |
| tree | ab291cffc65280e58ac82470ba63fbcca7805165 /226/CH10/EX10.17 | |
| download | Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.tar.gz Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.tar.bz2 Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.zip | |
initial commit / add all books
Diffstat (limited to '226/CH10/EX10.17')
| -rwxr-xr-x | 226/CH10/EX10.17/example17_sce.sce | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/226/CH10/EX10.17/example17_sce.sce b/226/CH10/EX10.17/example17_sce.sce new file mode 100755 index 000000000..1f691a734 --- /dev/null +++ b/226/CH10/EX10.17/example17_sce.sce @@ -0,0 +1,11 @@ +//chapter 10
+//example 10.17
+//page 424
+printf("\n")
+printf("given")
+Vdd=50;Rd=10;R2=1*10^6;rDS=.25;
+Id=Vdd/Rd
+disp(" from transfer curve at Id=5 and Vgs=5.7")
+Vgs=5.7;
+R1=((Vdd-Vgs)*R2)/Vgs//use 6.8Mohm to make Vgs>5.7V to ensure that the FET is biased on
+Vds=Id*rDS
\ No newline at end of file |