initial commit / add all books

12 files changed, 184 insertions, 0 deletions

diff --git a/135/CH7/EX7.1/7_1.JPG b/135/CH7/EX7.1/7_1.JPG
new file mode 100755
index 000000000..ddd0f0967
--- /dev/null
+++ b/135/CH7/EX7.1/7_1.JPG
diff --git a/135/CH7/EX7.1/EX1.sce b/135/CH7/EX7.1/EX1.sce
new file mode 100755
index 000000000..e96969d94
--- /dev/null
+++ b/135/CH7/EX7.1/EX1.sce
@@ -0,0 +1,10 @@
+// Example 7.1: Transfer curve

+clc, clear

+IDSS=12; // in mili-amperes

+VP=-5; // in volts

+// Plotting transfer curve

+VGS=[0:-0.01:VP]; // Gate source voltage in volts

+// Using Shockley's equation

+ID=IDSS*(1-VGS/VP)^2; // Drain current in mili-amperes

+plot(VGS,ID);

+xtitle("Transfer Curve","VGS (V)","ID (mA)");
\ No newline at end of file
diff --git a/135/CH7/EX7.2/EX2.sce b/135/CH7/EX7.2/EX2.sce
new file mode 100755
index 000000000..caab35349
--- /dev/null
+++ b/135/CH7/EX7.2/EX2.sce
@@ -0,0 +1,19 @@
+// Example 7.2: (a) Region of operation

+//              (b) Region of operation  

+//              (c) Region of operation

+clc, clear

+VT=2; // in volts

+VGS=3; // in volts

+disp(VGS-VT,"VGS - VT (V)");

+

+disp("Part (a)");

+disp(0.5,"VDS (V) =");

+disp("Since VDS < VGS - VT, therefore transistor is in ohmic region.");

+

+disp("Part (b)");

+disp(1,"VDS (V) =");

+disp("Since VDS = VGS - VT, therefore transistor is in saturation region.");

+

+disp("Part (c)");

+disp(5,"VDS (V) =");

+disp("Since VDS > VGS - VT, therefore transistor is in saturation region.");
\ No newline at end of file
diff --git a/135/CH7/EX7.3/EX3.sce b/135/CH7/EX7.3/EX3.sce
new file mode 100755
index 000000000..81775c5e6
--- /dev/null
+++ b/135/CH7/EX7.3/EX3.sce
@@ -0,0 +1,14 @@
+// Example 7.3: IDQ, VDSQ

+clc, clear

+IDSS=12; // in mili-amperes

+VP=-4; // in volts

+// From Fig. 7.28

+VDD=12; // in volts

+RD=1.2; // in kilo-ohms

+// Since IG=0

+VGS=-1.5; // in volts

+// Using Shockley's equation

+ID=IDSS*(1-VGS/VP)^2; // Drain current in mili-amperes

+VDS=VDD-ID*RD; // in volts

+disp(ID,"IDQ (mA) =");

+disp(VDS,"VDSQ (V) =");
\ No newline at end of file
diff --git a/135/CH7/EX7.4/7_4.JPG b/135/CH7/EX7.4/7_4.JPG
new file mode 100755
index 000000000..c1eb0021f
--- /dev/null
+++ b/135/CH7/EX7.4/7_4.JPG
diff --git a/135/CH7/EX7.4/EX4.sce b/135/CH7/EX7.4/EX4.sce
new file mode 100755
index 000000000..6405c498f
--- /dev/null
+++ b/135/CH7/EX7.4/EX4.sce
@@ -0,0 +1,35 @@
+// Example 7.4: VDSQ, IDSQ, VD, VS

+clc, clear

+IDSS=6e-3; // in amperes

+VP=-6; // in volts

+// From Fig. 7.31

+VDD=12; // in volts

+RD=2.2e3; // in ohms

+RS=1.6e3; // in ohms

+// Plotting transfer characteristics

+VGS=[0:-0.01:VP]; // Gate source voltage in volts

+// Using Shockley's equation

+ID=IDSS*(1-VGS/VP)^2; // Drain current in amperes

+ID=ID*1e3; // Drain current in mili-amperes

+plot(VGS,ID);

+xtitle("Transfer Characteristics","VGS (V)","ID (mA)");

+// Plotting bias line

+// From gate source circuit

+ID=-VGS/RS; // Source current in amperes

+ID=ID*1e3; // Source current in mili-amperes

+plot(VGS,ID,"RED");

+// Intersection of transfer characteristics with the bias curve

+// Putting VGS = -ID*RS in Shockley's equation and solving, we get ID^2*RS^2 + (2*RS*VP - VP^2/IDSS)*ID + VP^2

+// Solving the equation

+p_eq = poly([VP^2 (2*RS*VP-VP^2/IDSS) RS^2],"x","coeff");

+p_roots= roots(p_eq);

+IDQ=p_roots(1); // in amperes

+// Writing the KVL for the output loop

+VDSQ=VDD-IDQ*(RD+RS); // in volts

+VS=IDQ*RS; // in volts

+VD=VDSQ+VS; // in volts

+IDQ=IDQ*1e3; // in mili-amperes

+disp(VDSQ,"VDSQ (V) =");

+disp(IDQ,"IDQ (mA) =");

+disp(VD,"VD (V) =");

+disp(VS,"VS (V) =");
\ No newline at end of file
diff --git a/135/CH7/EX7.5/7_5.JPG b/135/CH7/EX7.5/7_5.JPG
new file mode 100755
index 000000000..2d7128229
--- /dev/null
+++ b/135/CH7/EX7.5/7_5.JPG
diff --git a/135/CH7/EX7.5/EX5.sce b/135/CH7/EX7.5/EX5.sce
new file mode 100755
index 000000000..63041bc53
--- /dev/null
+++ b/135/CH7/EX7.5/EX5.sce
@@ -0,0 +1,36 @@
+// Example 7.5: Operating point

+clc, clear

+VP=-5; // in volts

+IDSS=12e-3; // in amperes

+// From Fig. 7.34(a)

+VDD=18; // in volts

+R1=400; // in kilo-ohms

+R2=90; // in kilo-ohms

+RD=2e3; // in ohms

+RS=2e3; // in ohms

+// Applying Thevnin's theorem to obtain simplified circuit in Fig. 7.34(b)

+VGG=VDD*R2/(R1+R2); // in volts

+// Plotting transfer characteristics

+VGS=[VGG:-0.01:VP]; // Gate source voltage in volts

+// Using Shockley's equation

+ID=IDSS*(1-VGS/VP)^2; // Drain current in amperes

+ID=ID*1e3; // Drain current in mili-amperes

+plot2d(VGS,ID,rect=[-5,0,3,12]);

+xtitle("Transfer Characteristics","VGS (V)","ID (mA)");

+// Plotting bias line

+// From the KVL for the gate-loop

+ID=(-VGS+VGG)/RS; // Source current in amperes

+ID=ID*1e3; // Source current in mili-amperes

+plot(VGS,ID,"RED");

+// Intersection of transfer curve with the bias curve

+// Putting VGS = VGG-ID*RS in Shockley's equation and solving, we get

+// ID^2*RS^2 + (2*RS*VP - 2*VGG*RS - VP^2/IDSS)*ID + (VGG-VP)^2

+// Solving the equation

+p_eq = poly([(VGG-VP)^2 (2*RS*VP-2*VGG*RS-VP^2/IDSS) RS^2],"x","coeff");

+p_roots= roots(p_eq);

+IDQ=p_roots(1); // in amperes

+// Writing the KVL for the drain source loop

+VDSQ=VDD-IDQ*(RD+RS); // in volts

+IDQ=IDQ*1e3; // in mili-amperes

+disp(VDSQ,"VDSQ (V) =");

+disp(IDQ,"IDQ (mA) =");
\ No newline at end of file
diff --git a/135/CH7/EX7.6/7_6.JPG b/135/CH7/EX7.6/7_6.JPG
new file mode 100755
index 000000000..149ce8ae2
--- /dev/null
+++ b/135/CH7/EX7.6/7_6.JPG
diff --git a/135/CH7/EX7.6/EX6.sce b/135/CH7/EX7.6/EX6.sce
new file mode 100755
index 000000000..b573fbb8c
--- /dev/null
+++ b/135/CH7/EX7.6/EX6.sce
@@ -0,0 +1,31 @@
+// Example 7.6: VDSQ, IDQ

+clc, clear

+ID=6e-3; // in amperes

+VGS=8; // in volts

+VT=3; // in volts

+// From Fig. 7.37(a)

+VDD=12; // in volts

+RD=2e3; // in ohms

+// Plotting transfer curve

+k=ID/(VGS-VT)^2; // in amperes per volt square

+VGS=[3:0.01:VDD]; // Gate source voltage in volts

+ID=k*(VGS-VT)^2; // Drain current in amperes ............ (i)

+ID=ID*1e3; // Drain current in mili-amperes

+plot(VGS,ID);

+xtitle("Transfer Curve","VGS (V)","ID (mA)");

+// Plotting bias line

+// From the simplified dc equivalent circuit in Fig. 7.37(b)

+VGS=[0:0.01:VDD]; // Gate source voltage in volts

+ID=(VDD-VGS)/RD; // Source current in amperes

+ID=ID*1e3; // Source current in mili-amperes

+plot(VGS,ID,"RED");

+// Intersection of transfer curve with the bias curve

+// Putting VGS = VDD-ID*RD in equation (i) and solving, we get ID^2*RD^2 + (2*RD*VT - 2*VDD*RD - 1/k)*ID + (VDD-VT)^2

+// Solving the equation

+p_eq = poly([(VDD-VT)^2 (2*RD*VT-2*VDD*RD-1/k) RD^2],"x","coeff");

+p_roots= roots(p_eq);

+IDQ=p_roots(1); // in amperes

+VGSQ=VDD-IDQ*RD; // in volts

+IDQ=IDQ*1e3; // in mili-amperes

+disp(VGSQ,"VDSQ (V) =");

+disp(IDQ,"IDQ (mA) =");
\ No newline at end of file
diff --git a/135/CH7/EX7.7/7_7.JPG b/135/CH7/EX7.7/7_7.JPG
new file mode 100755
index 000000000..59e4a3a53
--- /dev/null
+++ b/135/CH7/EX7.7/7_7.JPG
diff --git a/135/CH7/EX7.7/EX7.sce b/135/CH7/EX7.7/EX7.sce
new file mode 100755
index 000000000..5a41039cb
--- /dev/null
+++ b/135/CH7/EX7.7/EX7.sce
@@ -0,0 +1,39 @@
+// Example 7.7: IDQ, VDSQ, VGSQ

+clc, clear

+ID=5e-3; // in amperes

+VGS=6; // in volts

+VT=3; // in volts

+// From Fig. 7.39(a)

+VDD=24; // in volts

+R1=10; // in mega-ohms

+R2=6.8; // in mega-ohms

+RD=2.2e3; // in ohms

+RS=0.75e3; // in ohms

+// Applying Thevnin's theorem to obtain simplified circuit in Fig. 7.39(b)

+VGG=VDD*R2/(R1+R2); // in volts

+// Plotting transfer characteristics

+k=ID/(VGS-VT)^2; // in amperes per volt square

+VGS=[3:0.01:VGG]; // Gate source voltage in volts

+ID=k*(VGS-VT)^2; // Drain current in amperes ............ (i)

+ID=ID*1e3; // Drain current in mili-amperes

+plot(VGS,ID);

+xtitle("Transfer Characteristics","VGS (V)","ID (mA)");

+// Plotting bias line

+VGS=[0:0.01:VGG]; // Gate source voltage in volts

+// Writing KVL for the gate-source loop

+ID=(VGG-VGS)/RS; // Source current in amperes

+ID=ID*1e3; // Source current in mili-amperes

+plot(VGS,ID,"RED");

+// Intersection of transfer curve with the bias curve

+// Putting VGS = VGG-ID*RD in equation (i) and solving, we get ID^2*RS^2 + (2*RS*VT - 2*VGG*RS - 1/k)*ID + (VGG-VT)^2

+// Solving the equation

+p_eq = poly([(VGG-VT)^2 (2*RS*VT-2*VGG*RS-1/k) RS^2],"x","coeff");

+p_roots= roots(p_eq);

+IDQ=p_roots(1); // in amperes

+VGSQ=VGG-IDQ*RS; // in volts

+// From the output circuit

+VDSQ=VDD-IDQ*(RD+RS); // in volts

+IDQ=IDQ*1e3; // in mili-amperes

+disp(IDQ,"IDQ (mA) =");

+disp(VDSQ,"VDSQ (V) =");

+disp(VGSQ,"VGSQ (V) =");
\ No newline at end of file