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| author | hardythe1 | 2015-05-05 14:21:39 +0530 |
|---|---|---|
| committer | hardythe1 | 2015-05-05 14:21:39 +0530 |
| commit | 435840cef00c596d9e608f9eb2d96f522ea8505a (patch) | |
| tree | 4c783890c984c67022977ca98432e5e4bab30678 /Op-amp_and_linear_integrated_circuits_/Chapter_6.ipynb | |
| parent | aa1863f344766ca7f7c20a395e58d0fb23c52130 (diff) | |
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Diffstat (limited to 'Op-amp_and_linear_integrated_circuits_/Chapter_6.ipynb')
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diff --git a/Op-amp_and_linear_integrated_circuits_/Chapter_6.ipynb b/Op-amp_and_linear_integrated_circuits_/Chapter_6.ipynb new file mode 100755 index 00000000..3aa928b8 --- /dev/null +++ b/Op-amp_and_linear_integrated_circuits_/Chapter_6.ipynb @@ -0,0 +1,117 @@ +{
+ "metadata": {
+ "name": ""
+ },
+ "nbformat": 3,
+ "nbformat_minor": 0,
+ "worksheets": [
+ {
+ "cells": [
+ {
+ "cell_type": "heading",
+ "level": 1,
+ "metadata": {},
+ "source": [
+ "Chapter 6: Digitally Controlled Frequency Synthesizers : PLLs"
+ ]
+ },
+ {
+ "cell_type": "heading",
+ "level": 2,
+ "metadata": {},
+ "source": [
+ "example 6.1, Page No. 247"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "collapsed": false,
+ "input": [
+ "# PLL circuit parameters(refere fig. 6.13)\n",
+ "\n",
+ "import math\n",
+ "#Variable declaration\n",
+ "Ct = 0.005 *10**-6 # external capacitor for VCO\n",
+ "Rt = 10*10**3 # external resistance for VCO\n",
+ "V = 20.0 # supply voltage(V_positive - V_negative) \n",
+ "C = 10*10**-6 # capacitance\n",
+ "\n",
+ "#Calculations\n",
+ "#(i)\n",
+ "fout = 0.25/(Rt*Ct)\n",
+ "\n",
+ "#(ii)\n",
+ "fL = 8*fout/V\n",
+ "\n",
+ "#(iii)\n",
+ "fC = fL/(2*math.pi*3.6*10**3*C)\n",
+ "fC = math.sqrt(fC)\n",
+ "\n",
+ "#in kHz\n",
+ "fout = fout/10**3\n",
+ "fL = fL/10**3\n",
+ "\n",
+ "#Result\n",
+ "print(\"(i)free running frequency, fout = %.0fkHz\\n(ii)Lock range, fL = +/-%.0f kHz\\n(iii)Calpture range, fC = +/-%d Hz\"%(fout,fL,fC))"
+ ],
+ "language": "python",
+ "metadata": {},
+ "outputs": [
+ {
+ "output_type": "stream",
+ "stream": "stdout",
+ "text": [
+ "(i)free running frequency, fout = 5kHz\n",
+ "(ii)Lock range, fL = +/-2 kHz\n",
+ "(iii)Calpture range, fC = +/-94 kHz\n"
+ ]
+ }
+ ],
+ "prompt_number": 9
+ },
+ {
+ "cell_type": "heading",
+ "level": 2,
+ "metadata": {},
+ "source": [
+ "example 6.2, Page No. 254"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "collapsed": false,
+ "input": [
+ "# Digital frequency synthesizer\n",
+ "\n",
+ "import math\n",
+ "#Variable declaration\n",
+ "R = 4 # resolution of digital frequency synthesizer\n",
+ "Fm = 200*10**3 # maximum frequency output\n",
+ "\n",
+ "#Calculations\n",
+ "fclk = Fm*2.2\n",
+ "k = fclk/R\n",
+ "n = math.log(k)/math.log(2)\n",
+ "\n",
+ "#Result\n",
+ "print(\"frequency of reference oscillator = %.0f kHz\\nno of bits required = %.0f\"%(fclk/1000,math.ceil(n)))"
+ ],
+ "language": "python",
+ "metadata": {},
+ "outputs": [
+ {
+ "output_type": "stream",
+ "stream": "stdout",
+ "text": [
+ "frequency of reference oscillator = 440 kHz\n",
+ "no of bits required = 17\n"
+ ]
+ }
+ ],
+ "prompt_number": 13
+ }
+ ],
+ "metadata": {}
+ }
+ ]
+}
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