Added(A)/Deleted(D) following books

 A  Analog_Electronics_by_U._A._Bakshi_And_A._P._Godse/chapter1.ipynb
A  Analog_Electronics_by_U._A._Bakshi_And_A._P._Godse/chapter2.ipynb
A  Analog_Electronics_by_U._A._Bakshi_And_A._P._Godse/chapter3.ipynb
A  Analog_Electronics_by_U._A._Bakshi_And_A._P._Godse/chapter4.ipynb
A  Analog_Electronics_by_U._A._Bakshi_And_A._P._Godse/chapter5.ipynb
A  Analog_Electronics_by_U._A._Bakshi_And_A._P._Godse/chapter6.ipynb
A  Analog_Electronics_by_U._A._Bakshi_And_A._P._Godse/screenshots/CloseLoopVoltageGain3-5.png
A  Analog_Electronics_by_U._A._Bakshi_And_A._P._Godse/screenshots/ValueOfResistance3_9.png
A  Analog_Electronics_by_U._A._Bakshi_And_A._P._Godse/screenshots/requiredResistance3_8.png
A  Electrical_Engineering_Fundamentals_by__Del_Toro_Vincent_/CHAPTER01_2.ipynb
A  Electrical_Engineering_Fundamentals_by__Del_Toro_Vincent_/CHAPTER02_2.ipynb
A  Electrical_Engineering_Fundamentals_by__Del_Toro_Vincent_/CHAPTER03_2.ipynb
A  Electrical_Engineering_Fundamentals_by__Del_Toro_Vincent_/CHAPTER04_2.ipynb
A  Electrical_Engineering_Fundamentals_by__Del_Toro_Vincent_/CHAPTER07_2.ipynb
A  Electrical_Engineering_Fundamentals_by__Del_Toro_Vincent_/CHAPTER09_2.ipynb
A  Electrical_Engineering_Fundamentals_by__Del_Toro_Vincent_/CHAPTER11_2.ipynb
A  Electrical_Engineering_Fundamentals_by__Del_Toro_Vincent_/CHAPTER15_2.ipynb
A  Electrical_Engineering_Fundamentals_by__Del_Toro_Vincent_/CHAPTER16_2.ipynb
A  Electrical_Engineering_Fundamentals_by__Del_Toro_Vincent_/CHAPTER18_2.ipynb
A  Electrical_Engineering_Fundamentals_by__Del_Toro_Vincent_/CHAPTER19_2.ipynb
A  Electrical_Engineering_Fundamentals_by__Del_Toro_Vincent_/CHAPTER20_2.ipynb
A  Electrical_Engineering_Fundamentals_by__Del_Toro_Vincent_/CHAPTER23_2.ipynb
A  Electrical_Engineering_Fundamentals_by__Del_Toro_Vincent_/CHAPTER24_2.ipynb
A  Electrical_Engineering_Fundamentals_by__Del_Toro_Vincent_/screenshots/Capture02_2.png
A  Electrical_Engineering_Fundamentals_by__Del_Toro_Vincent_/screenshots/Capture04_2.png
A  Electrical_Engineering_Fundamentals_by__Del_Toro_Vincent_/screenshots/Capture20_2.png
A  Electronics_Circuits_and_Systems_by_Y._N._Bapat/Ch1.ipynb
A  Electronics_Circuits_and_Systems_by_Y._N._Bapat/Ch10.ipynb
A  Electronics_Circuits_and_Systems_by_Y._N._Bapat/Ch11.ipynb
A  Electronics_Circuits_and_Systems_by_Y._N._Bapat/Ch12.ipynb
A  Electronics_Circuits_and_Systems_by_Y._N._Bapat/Ch13.ipynb
A  Electronics_Circuits_and_Systems_by_Y._N._Bapat/Ch14.ipynb
A  Electronics_Circuits_and_Systems_by_Y._N._Bapat/Ch2.ipynb
A  Electronics_Circuits_and_Systems_by_Y._N._Bapat/Ch3.ipynb
A  Electronics_Circuits_and_Systems_by_Y._N._Bapat/Ch4.ipynb
A  Electronics_Circuits_and_Systems_by_Y._N._Bapat/Ch5.ipynb
A  Electronics_Circuits_and_Systems_by_Y._N._Bapat/Ch6.ipynb
A  Electronics_Circuits_and_Systems_by_Y._N._Bapat/Ch7.ipynb
A  Electronics_Circuits_and_Systems_by_Y._N._Bapat/Ch8.ipynb
A  Electronics_Circuits_and_Systems_by_Y._N._Bapat/Ch9.ipynb
A  Electronics_Circuits_and_Systems_by_Y._N._Bapat/screenshots/AntilogOpamp13.png
A  Electronics_Circuits_and_Systems_by_Y._N._Bapat/screenshots/LogOpamp13.png
A  Electronics_Circuits_and_Systems_by_Y._N._Bapat/screenshots/OutPutLogAmp13.png
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER10_10.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER10_11.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER13_10.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER13_11.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER14_10.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER14_11.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER15_10.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER15_11.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER16_10.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER16_11.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER17_10.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER17_9.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER18_10.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER18_11.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER20_10.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER20_9.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER22_10.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER22_9.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER23_10.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER23_11.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER25_10.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER25_9.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER28_10.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER28_9.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER2_10.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER2_11.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER32_10.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER32_9.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER36_10.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER36_11.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER9_10.ipynb
A  Manufacturing_Engineering_&_Technology_by__S._Kalpakjian_and_S._R._Schmid/CHAPTER9_11.ipynb
A  Strength_Of_Materials_by_S_S_Bhavikatti/chapter_no.10_3.ipynb
A  Strength_Of_Materials_by_S_S_Bhavikatti/chapter_no.1_3.ipynb
A  Strength_Of_Materials_by_S_S_Bhavikatti/chapter_no.2_3.ipynb
A  Strength_Of_Materials_by_S_S_Bhavikatti/chapter_no.3_3.ipynb
A  Strength_Of_Materials_by_S_S_Bhavikatti/chapter_no.4_3.ipynb
A  Strength_Of_Materials_by_S_S_Bhavikatti/chapter_no.5_3.ipynb
A  Strength_Of_Materials_by_S_S_Bhavikatti/chapter_no.6_3.ipynb
A  Strength_Of_Materials_by_S_S_Bhavikatti/chapter_no.7_3.ipynb
A  Strength_Of_Materials_by_S_S_Bhavikatti/chapter_no.8_3.ipynb
A  Strength_Of_Materials_by_S_S_Bhavikatti/chapter_no.9_3.ipynb
A  Strength_Of_Materials_by_S_S_Bhavikatti/screenshots/B.M.D_1_2.JPG
A  Strength_Of_Materials_by_S_S_Bhavikatti/screenshots/S.F.D_1_2.jpg
A  Strength_Of_Materials_by_S_S_Bhavikatti/screenshots/S.F.D_2_2.jpg
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/Chapter10_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/Chapter28_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/Chapter29_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter11_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter12_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter13_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter14_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter15_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter16_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter17_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter18_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter19_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter1_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter20_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter21_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter22_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter23_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter24_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter25_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter26_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter27_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter2_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter3_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter4_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter5_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter6_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter7_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter8_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/chapter9_2.ipynb
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/screenshots/image11_1.png
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/screenshots/image12_1.png
A  principle_of_physics_by_V.K.MEHTA_,_ROHIT_MEHTA_/screenshots/image13_1.png

1 files changed, 596 insertions, 0 deletions

diff --git a/Electronics_Circuits_and_Systems_by_Y._N._Bapat/Ch9.ipynb b/Electronics_Circuits_and_Systems_by_Y._N._Bapat/Ch9.ipynb
new file mode 100644
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+++ b/Electronics_Circuits_and_Systems_by_Y._N._Bapat/Ch9.ipynb
@@ -0,0 +1,596 @@
+{
+ "cells": [
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    "# Chapter 9 - Digital Circuits and Logic Families"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    "## Example 9_1 Page No. 278"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 3,
+   "metadata": {
+    "collapsed": false
+   },
+   "outputs": [
+    {
+     "name": "stdout",
+     "output_type": "stream",
+     "text": [
+      "VCC= 5.00  volts\n",
+      "RB= 10000.00  ohm\n",
+      "RL= 1000.00  ohm\n",
+      "VCS= 0.20  volts\n",
+      "VBS= 0.80  volts\n",
+      "V_gamma= 0.60  volts\n",
+      "ICS = (VCC-VCS)/RL=4.80e-03  ampere\n",
+      "vi= 5.00  volts\n",
+      "IBS=(vi-VBS)/RB=4.20e-04  ampere\n",
+      "Beta_Fmin=ICS/IBS= 11.43\n"
+     ]
+    }
+   ],
+   "source": [
+    "from __future__ import division  \n",
+    "VCC=5\n",
+    "print \"VCC= %0.2f\"%(VCC),\" volts\" #  voltage supply  \n",
+    "RB=10*10**(3)\n",
+    "print \"RB= %0.2f\"%(RB),\" ohm\"  # Base-resistance\n",
+    "RL=1*10**(3)\n",
+    "print \"RL= %0.2f\"%(RL),\" ohm\"  # Load resistance\n",
+    "VCS=0.2\n",
+    "print \"VCS= %0.2f\"%(VCS),\" volts\" # collector saturated voltage \n",
+    "VBS=0.8\n",
+    "print \"VBS= %0.2f\"%(VBS),\" volts\" # Base voltage at saturation \n",
+    "V_gamma=0.6\n",
+    "print \"V_gamma= %0.2f\"%(V_gamma),\" volts\" #  Threshold or cut-in voltage\n",
+    "ICS=(VCC-VCS)/RL\n",
+    "print \"ICS = (VCC-VCS)/RL=%0.2e\"%(ICS),\" ampere\" #Saturation collector current of transistor T1\n",
+    "vi=5\n",
+    "print \"vi= %0.2f\"%(vi),\" volts\" #  Input voltage \n",
+    "IBS=(vi-VBS)/RB\n",
+    "print \"IBS=(vi-VBS)/RB=%0.2e\"%(IBS),\" ampere\" # Forward base drive required to sustain ICS\n",
+    "Beta_Fmin=ICS/IBS\n",
+    "print \"Beta_Fmin=ICS/IBS= %0.2f\"%(Beta_Fmin) # Common-emitter current gain\n",
+    "\n",
+    "#NOTE:  Correct formulae for ICS=(VCC-VCS)/RL\n",
+    "# but in book it is written wrong as ICS=(VCC-VCS)/RB but had calculated ans (in book) according to correct formulae ICS=(VCC-VCS)/RL"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    "## Example 9_2 Page No. 279"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 3,
+   "metadata": {
+    "collapsed": false
+   },
+   "outputs": [
+    {
+     "name": "stdout",
+     "output_type": "stream",
+     "text": [
+      "VD= 0.70  V\n",
+      "part(i)\n",
+      "vA= 0.00  V\n",
+      "vB= 0.00  V\n",
+      "vX=0.00  V\n",
+      "part(ii)\n",
+      "vA= 0.00  V\n",
+      "vB= 5.00  V\n",
+      "vX=vB-VD= 4.30  V\n",
+      "part(iii)\n",
+      "vA= 5.00  V\n",
+      "vB= 0.00  V\n",
+      "vX=vA-VD= 4.30  V\n",
+      "part(iv)\n",
+      "vA= 5.00  V\n",
+      "vB= 5.00  V\n",
+      "vX=vA-VD=vB-VD= 4.30  V\n"
+     ]
+    }
+   ],
+   "source": [
+    "from __future__ import division  \n",
+    "VD=0.7\n",
+    "print \"VD= %0.2f\"%(VD),\" V\" #  Diode voltage drop in conduction mode\n",
+    "\n",
+    "print \"part(i)\"# part(i)of question\n",
+    "vA=0\n",
+    "print \"vA= %0.2f\"%(vA),\" V\" #   Input voltage1 of diode OR logic gate\n",
+    "vB=0\n",
+    "print \"vB= %0.2f\"%(vB),\" V\" #  Input voltage2 of diode OR logic gate\n",
+    "vX=0 # Since both input voltages vA=vB=0V\n",
+    "print \"vX=%0.2f\"%(vX),\" V\" #  Output voltage of diode OR logic gate for part(i)\n",
+    "\n",
+    "print \"part(ii)\"# part(ii)of question\n",
+    "vA=0\n",
+    "print \"vA= %0.2f\"%(vA),\" V\" #  Input voltage1 of diode OR logic gate\n",
+    "vB=5\n",
+    "print \"vB= %0.2f\"%(vB),\" V\" #  Input voltage2 of diode OR logic gate for  SECOND CASE: when vA=0V and vB=5V\n",
+    "vX=vB-VD\n",
+    "print \"vX=vB-VD= %0.2f\"%(vX),\" V\" #  Output voltage of diode OR logic gate for  SECOND CASE\n",
+    "\n",
+    "print \"part(iii)\"# part(iii)of question\n",
+    "vA=5\n",
+    "print \"vA= %0.2f\"%(vA),\" V\" #  Input voltage1 of diode OR logic gate for  THIRD CASE  when vA=5V and vB=0V\n",
+    "vB=0\n",
+    "print \"vB= %0.2f\"%(vB),\" V\" #  Input voltage2 of diode OR logic gate\n",
+    "vX=vA-VD\n",
+    "print \"vX=vA-VD= %0.2f\"%(vX),\" V\" #  Output voltage of diode OR logic gate for  THIRD CASE\n",
+    "\n",
+    "print \"part(iv)\"# part(iv)of question\n",
+    "vA=(+5)\n",
+    "print \"vA= %0.2f\"%(vA),\" V\" #  Input voltage1 of diode OR logic gate\n",
+    "vB=(+5)\n",
+    "print \"vB= %0.2f\"%(vB),\" V\" #  Input voltage2 of diode OR logic gate\n",
+    "vX=vA-VD # Since both diodes D1 and D2 are conducting\n",
+    "vX=vB-VD \n",
+    "print \"vX=vA-VD=vB-VD= %0.2f\"%(vX),\" V\" #  Output voltage of diode OR logic gate for FOURTH CASE: when vA=5V and vB=5V"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    "## Example 9_3 Page No. 281"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 4,
+   "metadata": {
+    "collapsed": false
+   },
+   "outputs": [
+    {
+     "name": "stdout",
+     "output_type": "stream",
+     "text": [
+      "VD= 0.70  V\n",
+      "part(i)\n",
+      "vA= 0.00  V\n",
+      "vB= 0.00  V\n",
+      "vX=VD=0.70  V\n",
+      "part(ii)\n",
+      "vA= 0.00  V\n",
+      "vB= 5.00  V\n",
+      "vX=VD 0.70  V\n",
+      "part(iii)\n",
+      "vA= 5.00  V\n",
+      "vB= 0.00  V\n",
+      "vX= 0.70  V\n",
+      "part(iv)\n",
+      "vA= 5.00  V\n",
+      "vB= 5.00  V\n",
+      "vX = vA = vB= 5.00  V\n"
+     ]
+    }
+   ],
+   "source": [
+    "from __future__ import division  \n",
+    "VD=0.7\n",
+    "print \"VD= %0.2f\"%(VD),\" V\" #  Diode voltage drop in conduction mode\n",
+    "\n",
+    "print \"part(i)\"\n",
+    "vA=0\n",
+    "print \"vA= %0.2f\"%(vA),\" V\" #  Input voltage of diode AND logic gate\n",
+    "vB=0\n",
+    "print \"vB= %0.2f\"%(vB),\" V\" #  Input voltage2 of diode  AND logic gate\n",
+    "\n",
+    "vX=VD # Since both input voltages vA=vB=0V\n",
+    "print \"vX=VD=%0.2f\"%(vX),\" V\" #  Output voltage of diode  AND logic gate for FIRST CASE: when vA=0V and vB=0V\n",
+    "\n",
+    "print \"part(ii)\"\n",
+    "vA=0\n",
+    "print \"vA= %0.2f\"%(vA),\" V\" #  Input voltage of diode AND logic gate\n",
+    "vB=5\n",
+    "print \"vB= %0.2f\"%(vB),\" V\" #  Input voltage2 of diode AND logic gate for  SECOND CASE: when vA=0V and vB=5V\n",
+    "vX=VD #due to diode A which is  conducting and the Diode B is reverse biased with a voltage VD-VB=0.7-5=-4.3\n",
+    "print \"vX=VD %0.2f\"%(vX),\" V\"\n",
+    "#due to diode B which is conducting\n",
+    "\n",
+    "\n",
+    "\n",
+    "print \"part(iii)\"\n",
+    "vA=5\n",
+    "print \"vA= %0.2f\"%(vA),\" V\" #  Input voltage for  THIRD CASE  when vA=5V and vB=0V\n",
+    "vB=0\n",
+    "print \"vB= %0.2f\"%(vB),\" V\" #  Input voltage2 of diode  AND logic gate\n",
+    "vX = VD#due to diode B which is  conducting and the Diode A is reverse biased with a voltage VD-VA=0.7-5=-4.3\n",
+    "print \"vX= %0.2f\"%(vX),\" V\"\n",
+    "\n",
+    "print \"part(iv)\"\n",
+    "vA=5\n",
+    "print \"vA= %0.2f\"%(vA),\" V\" #  Input voltage forfourth CASE  when vA=5V and vB=5V\n",
+    "vB=5\n",
+    "print \"vB= %0.2f\"%(vB),\" V\" #  Input voltage2 of diode AND logic gate for  CASE: when vA=0V and vB=5V\n",
+    "vX=vA # Since both diodes D1 and D2 are Non-conducting, so no voltage drop across'R'(resistor)\n",
+    "print \"vX = vA = vB= %0.2f\"%(vX),\" V\" #  Output voltage of diode  AND logic gate for FOURTH CASE: when vA=5V and vB=5V"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    "## Example 9_6  Page No. 285"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 5,
+   "metadata": {
+    "collapsed": false
+   },
+   "outputs": [
+    {
+     "name": "stdout",
+     "output_type": "stream",
+     "text": [
+      "VIL= 0.60  V\n",
+      "VIH= 0.75  V\n",
+      "VOL= 0.20  V\n",
+      "VOH= 1.00  V\n",
+      "NML=VIL-VOL= 0.40  V\n",
+      "NMH=VOH-VIH= 0.25  V\n"
+     ]
+    }
+   ],
+   "source": [
+    "from __future__ import division  \n",
+    "VIL=0.6\n",
+    "print \"VIL= %0.2f\"%(VIL),\" V\" #  Minimum input voltage level for which output is maximum\n",
+    "VIH=0.75\n",
+    "print \"VIH= %0.2f\"%(VIH),\" V\" #  Maximum input voltage level for which output is minimum\n",
+    "VOL=0.2\n",
+    "print \"VOL= %0.2f\"%(VOL),\" V\" #  Minimum output voltage level for  maximum input level\n",
+    "VOH=1\n",
+    "print \"VOH= %0.2f\"%(VOH),\" V\" #   Maximum output voltage level for   minimum input level\n",
+    "NML=VIL-VOL\n",
+    "print \"NML=VIL-VOL= %0.2f\"%(NML),\" V\" #  Low level noise immunities\n",
+    "NMH=VOH-VIH\n",
+    "print \"NMH=VOH-VIH= %0.2f\"%(NMH),\" V\" # High level noise immunities"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    "## Example 9_7 Page No. 287"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 4,
+   "metadata": {
+    "collapsed": false
+   },
+   "outputs": [
+    {
+     "name": "stdout",
+     "output_type": "stream",
+     "text": [
+      "IIL= -1.60e-03  A\n",
+      "IIH= 4.00e-05  A\n",
+      "IOL= 1.60e-02  A\n",
+      "IOH= -4.00e-04  A\n",
+      "Fan-out=abs((IOH/IIH)=abs((IOL/IIL))= 10.00\n"
+     ]
+    }
+   ],
+   "source": [
+    "from __future__ import division  \n",
+    "IIL=-1.6*10**(-3)\n",
+    "print \"IIL= %0.2e\"%(IIL),\" A\" #  Input sink Current of TTL driver\n",
+    "IIH=40*10**(-6)\n",
+    "print \"IIH= %0.2e\"%(IIH),\" A\" #  source (supply) reverse Current of TTL driver\n",
+    "IOL=16*10**(-3)\n",
+    "print \"IOL= %0.2e\"%(IOL),\" A\" #  Specified Maximum sink Current of TTL driver\n",
+    "IOH=-400*10**(-6)\n",
+    "print \"IOH= %0.2e\"%(IOH),\" A\" #  Specified Maximum source Current of TTL driver\n",
+    "Fan_out=abs((IOH/IIH))\n",
+    "print \"Fan-out=abs((IOH/IIH)=abs((IOL/IIL))= %0.2f\"%(Fan_out)# Fan-out of TTL"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    "## Example 9_8  Page No. 288"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 8,
+   "metadata": {
+    "collapsed": false
+   },
+   "outputs": [
+    {
+     "name": "stdout",
+     "output_type": "stream",
+     "text": [
+      "VIL= 0.80  V\n",
+      "VIH= 2.00  V\n",
+      "VOL= 0.40  V\n",
+      "VOH= 2.40  V\n",
+      "NML=VIL-VOL= 0.40  V\n",
+      "NMH=VOH-VIH= 0.40  V\n"
+     ]
+    }
+   ],
+   "source": [
+    "from __future__ import division  \n",
+    "VIL=0.8\n",
+    "print \"VIL= %0.2f\"%(VIL),\" V\" #  Minimum input voltage level for which output is maximum\n",
+    "VIH=2\n",
+    "print \"VIH= %0.2f\"%(VIH),\" V\" #  Maximum input voltage level for which output is minimum\n",
+    "VOL=0.4\n",
+    "print \"VOL= %0.2f\"%(VOL),\" V\" #  Minimum output voltage level for  maximum input level\n",
+    "VOH=2.4\n",
+    "print \"VOH= %0.2f\"%(VOH),\" V\" #   Maximum output voltage level for   minimum input level\n",
+    "NML=VIL-VOL\n",
+    "print \"NML=VIL-VOL= %0.2f\"%(NML),\" V\" #  Low level noise immunities\n",
+    "NMH=VOH-VIH\n",
+    "print \"NMH=VOH-VIH= %0.2f\"%(NMH),\" V\" # High level noise immunities"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    "## Example 9_9 Page No. 289"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 9,
+   "metadata": {
+    "collapsed": false
+   },
+   "outputs": [
+    {
+     "name": "stdout",
+     "output_type": "stream",
+     "text": [
+      "VIL= 1.00  V\n",
+      "VIH= 4.00  V\n",
+      "VOL= 0.50  V\n",
+      "VOH= 4.50  V\n",
+      "NML=VIL-VOL= 0.50  V\n",
+      "NMH=VOH-VIH= 0.50  V\n"
+     ]
+    }
+   ],
+   "source": [
+    "from __future__ import division  \n",
+    "VIL=1\n",
+    "print \"VIL= %0.2f\"%(VIL),\" V\" #  Minimum input voltage level for which output is maximum\n",
+    "VIH=4\n",
+    "print \"VIH= %0.2f\"%(VIH),\" V\" #  Maximum input voltage level for which output is minimum\n",
+    "VOL=0.5\n",
+    "print \"VOL= %0.2f\"%(VOL),\" V\" #  Minimum output voltage level for  maximum input level\n",
+    "VOH=4.5\n",
+    "print \"VOH= %0.2f\"%(VOH),\" V\" #   Maximum output voltage level for   minimum input level\n",
+    "NML=VIL-VOL\n",
+    "print \"NML=VIL-VOL= %0.2f\"%(NML),\" V\" #  Low level noise immunities\n",
+    "NMH=VOH-VIH\n",
+    "print \"NMH=VOH-VIH= %0.2f\"%(NMH),\" V\" # High level noise immunities"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    "## Example 9_10 Page No. 291"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 10,
+   "metadata": {
+    "collapsed": false
+   },
+   "outputs": [
+    {
+     "name": "stdout",
+     "output_type": "stream",
+     "text": [
+      "V_gamma= 0.60  volts\n",
+      "VEE= -5.20  volts\n",
+      "VBE3=VBE4=VBE5 0.70  volts\n",
+      "RE= 779.00  ohm\n",
+      "RL2= 220.00  ohm\n",
+      "RL3= 245.00  ohm\n",
+      "VREF= -1.29  volts\n",
+      "V(1)= -0.70  volts\n",
+      "V(0)= -1.70  volts\n",
+      "part(i)\n",
+      "VE=VREF-VBE3= -1.99  volts\n",
+      "IE=(VEE-VE)/RE= -0.00  A\n",
+      "IC3=IE= -0.00  A\n",
+      "vC3=IC3*RL3= -1.01  volts\n",
+      "vY=vC3-VBE5= -1.71  volts\n",
+      "vX=vC2-VBE4= -0.70  volts\n",
+      "Base -Emitter reverse voltage,VBEr=V(0)-VE= 0.29  volts\n",
+      "Transistor T1 and T2 off since VBEr < V_gamma\n",
+      "part(ii)\n",
+      "vY=VC3-VBE= -0.70  volts\n",
+      "VE=vB-VBE= -1.40  volts\n",
+      "VBE3=VREF-VE= 0.11  volts\n",
+      "VBE3 is smaller than V_gamma,hence T3 is off\n",
+      "IC2=(VEE-VE)/RE= -0.00  A\n",
+      "vC2=IC2*RL2= -1.07  volts\n",
+      "vX=vC2-VBE4= -1.77  volts\n",
+      "part(iii)\n",
+      "VE3=VE= -1.99  volts\n",
+      "VB3=VREF= -1.29  volts\n",
+      "IC3=(VEE-VE3)/RE= -0.00  A\n",
+      "VC3=IC3*RL3= -1.01  volts\n",
+      "VCB3=VC3-VB3= 0.28  volts\n",
+      "All parameters have appropriate signs for npn BJT hence BJT in active region\n"
+     ]
+    }
+   ],
+   "source": [
+    "from __future__ import division  \n",
+    "V_gamma=0.6\n",
+    "print \"V_gamma= %0.2f\"%(V_gamma),\" volts\" #Threshold voltage\n",
+    "VEE=-5.2\n",
+    "print \"VEE= %0.2f\"%(VEE),\" volts\" #  voltage supply \n",
+    "VBE3=0.7\n",
+    "VBE4=VBE3\n",
+    "VBE5=VBE3\n",
+    "print \"VBE3=VBE4=VBE5 %0.2f\"%(VBE3),\" volts\" #base-emitter voltage\n",
+    "RE=779\n",
+    "print \"RE= %0.2f\"%(RE),\" ohm\"  # Emitter-resistance\n",
+    "RL2=220\n",
+    "print \"RL2= %0.2f\"%(RL2),\" ohm\"  # Load resistance\n",
+    "RL3=245\n",
+    "print \"RL3= %0.2f\"%(RL3),\" ohm\"  # Load resistance\n",
+    "VREF=-1.29\n",
+    "print \"VREF= %0.2f\"%(VREF),\" volts\" # Reference- voltage \n",
+    "V_1=-0.7\n",
+    "print \"V(1)= %0.2f\"%(V_1),\" volts\" # Acceptable voltage for high logic  \n",
+    "V_0=-1.7\n",
+    "print \"V(0)= %0.2f\"%(V_0),\" volts\" # Acceptable voltage for low logic \n",
+    "\n",
+    "print \"part(i)\"# part(i)of question\n",
+    "VE=VREF-VBE3\n",
+    "print \"VE=VREF-VBE3= %0.2f\"%(VE),\" volts\" # Emitter- voltage  \n",
+    "IE=(VEE-VE)/RE\n",
+    "print \"IE=(VEE-VE)/RE= %0.2f\"%(IE),\" A\" #Emitter- Current\n",
+    "IC3=IE# since IC=IE neglecting IB\n",
+    "print \"IC3=IE= %0.2f\"%(IE),\" A\" #Collector- Current\n",
+    "vC3=IC3*RL3\n",
+    "print \"vC3=IC3*RL3= %0.2f\"%(vC3),\" volts\" # Collector- voltage \n",
+    "vY=vC3-VBE5\n",
+    "print \"vY=vC3-VBE5= %0.2f\"%(vY),\" volts\" # Emitter follower output voltage for vB=V(0) \n",
+    "vC2=0 \n",
+    "vX=vC2-VBE4\n",
+    "print \"vX=vC2-VBE4= %0.2f\"%(vX),\" volts\" # Emitter follower output voltage  for vB=V(0)  \n",
+    "VBEr=(V_0)-VE\n",
+    "print \"Base -Emitter reverse voltage,VBEr=V(0)-VE= %0.2f\"%(VBEr),\" volts\"#Base- Emitter junction reverse voltage ,this is sufficient to keep T1 and T2 off since threshold =0.6V\n",
+    "print \"Transistor T1 and T2 off since VBEr < V_gamma\" # Since VBEr < V_gamma hence T1 and T2 off\n",
+    "\n",
+    "print \"part(ii)\"# part(ii)of question\n",
+    "IC2=IE\n",
+    "VBE=0.7 \n",
+    "vB=V_1\n",
+    "IC3=0\n",
+    "VC3=0\n",
+    "vY=VC3-VBE5\n",
+    "print \"vY=VC3-VBE= %0.2f\"%(vY),\" volts\"# Emitter follower output voltage  for SECOND CASE for vB=V(1)  \n",
+    "VE=vB-VBE\n",
+    "print \"VE=vB-VBE= %0.2f\"%(VE),\" volts\" # Emitter- voltage   \n",
+    "VBE3=VREF-VE\n",
+    "print \"VBE3=VREF-VE= %0.2f\"%(VBE3),\" volts\"#Base- Emitter junction voltage\n",
+    "print \"VBE3 is smaller than V_gamma,hence T3 is off\"\n",
+    "IC2=(VEE-VE)/RE\n",
+    "print \"IC2=(VEE-VE)/RE= %0.2f\"%(IC2),\" A\" #Collector- Current for T2(transistor)\n",
+    "vC2=IC2*RL2\n",
+    "print \"vC2=IC2*RL2= %0.2f\"%(vC2),\" volts\" # Collector- voltage for T2\n",
+    "vX=vC2-VBE4\n",
+    "print \"vX=vC2-VBE4= %0.2f\"%(vX),\" volts\" # Emitter follower output voltage for vB=V(1)\n",
+    "\n",
+    "print \"part(iii)\"# part(iii)of question \n",
+    "VE3=-1.99\n",
+    "print \"VE3=VE= %0.2f\"%(VE3),\" volts\" #  Transistor T3 Emitter- voltage ,when T3 is conducting  \n",
+    "VB3=VREF\n",
+    "print \"VB3=VREF= %0.2f\"%(VB3),\" volts\" # Base- voltage when T3 is conducting\n",
+    "IC3=(VEE-VE3)/RE# Collector current for T3 neglecting IB\n",
+    "print \"IC3=(VEE-VE3)/RE= %0.2f\"%(IC3),\" A\" #Collector- Current\n",
+    "VC3=IC3*RL3\n",
+    "print \"VC3=IC3*RL3= %0.2f\"%(VC3),\" volts\" # Collector- voltage when T3 is conducting  \n",
+    "VCB3=VC3-VB3\n",
+    "print \"VCB3=VC3-VB3= %0.2f\"%(VCB3),\" volts\" # Base- voltage when T3 is conducting  \n",
+    "#All parameters have appropriate signs for npn BJT hence BJT in active region not in saturation in which VCB will have a (-)value\n",
+    "print \"All parameters have appropriate signs for npn BJT hence BJT in active region\"  \n",
+    "\n",
+    "\n",
+    "# NOTE: Author ha not used any symbol for Base- Emitter junction reverse voltage   But I have used 'VBEr' for it.\n",
+    "# ERROR :sign of IE is given wrong in the book in part(i) and sign of IC2 in part(ii)\n",
+    "# In part(i) Correct Formulae of vC3 is vC3 =IC3*RL3 but given in book is vC3 =(-)IC3*RL3  because author has  included the (-)ive sign or the polarity of IC3 in the formulae \n",
+    "# IN book in part(ii) mistakenly it  is written as vB=V_0 =-0.7 V but Correct expression is vB=V_1=-0.7 V because vB is at high at V_1=-0.7 V\n",
+    "# In part(ii) Author has used formulae vC2=-IC2*RL2  because he has included the (-)ive sign of the IC2  in the formulae  but I have used vC2=IC2*RL2 to remove any ambiguity in program"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    "## Example 9_11 Page No. 292"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 11,
+   "metadata": {
+    "collapsed": false
+   },
+   "outputs": [
+    {
+     "name": "stdout",
+     "output_type": "stream",
+     "text": [
+      "VIL= -1.48  V\n",
+      "VIH= -1.10  V\n",
+      "VOL= -1.63  V\n",
+      "VOH= -0.98  V\n",
+      "NML=VIL-VOL= 0.15  V\n",
+      "NMH=VOH-VIH= 0.12  V\n"
+     ]
+    }
+   ],
+   "source": [
+    "from __future__ import division  \n",
+    "VIL=-1.475\n",
+    "print \"VIL= %0.2f\"%(VIL),\" V\" #  Minimum input voltage level for which output is maximum\n",
+    "VIH=-1.105\n",
+    "print \"VIH= %0.2f\"%(VIH),\" V\" #  Maximum input voltage level for which output is minimum\n",
+    "VOL=-1.63\n",
+    "print \"VOL= %0.2f\"%(VOL),\" V\" #  Minimum output voltage level for  maximum input level\n",
+    "VOH=-0.98\n",
+    "print \"VOH= %0.2f\"%(VOH),\" V\" #   Maximum output voltage level for   minimum input level\n",
+    "NML=VIL-VOL\n",
+    "print \"NML=VIL-VOL= %0.2f\"%(NML),\" V\" #  Low level noise immunities\n",
+    "NMH=VOH-VIH\n",
+    "print \"NMH=VOH-VIH= %0.2f\"%(NMH),\" V\" # High level noise immunities"
+   ]
+  }
+ ],
+ "metadata": {
+  "kernelspec": {
+   "display_name": "Python 2",
+   "language": "python",
+   "name": "python2"
+  },
+  "language_info": {
+   "codemirror_mode": {
+    "name": "ipython",
+    "version": 2
+   },
+   "file_extension": ".py",
+   "mimetype": "text/x-python",
+   "name": "python",
+   "nbconvert_exporter": "python",
+   "pygments_lexer": "ipython2",
+   "version": "2.7.9"
+  }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 0
+}